IDT7025L15PF IDT, Integrated Device Technology Inc, IDT7025L15PF Datasheet - Page 18

• Manufacturer Part Number: IDT7025L15PF
• Description: IC SRAM 128KBIT 15NS 100TQFP
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of IDT7025L15PF

• Format - Memory: RAM
• Memory Type: SRAM - Dual Port, Asynchronous
• Memory Size: 128K (8K x 16)
• Speed: 15ns
• Interface: Parallel
• Voltage - Supply: 4.5 V ~ 5.5 V
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 7025L15PF

Truth Table II — Address BUSY
Arbitration
NOTES:
1. Pins BUSY
2. "L" if the inputs to the opposite port were stable prior to the address and enable inputs of this port. "H" if the inputs to the opposite port became stable after the address
3. Writes to the left port are internally ignored when BUSY
Functional Description
I/O pins that permit independent access for reads or writes to any location
in memory. The IDT7025 has an automatic power down feature controlled
by CE. The CE controls on-chip power down circuitry that permits the
respective port to go into a standby mode when not selected (CE = V
When a port is enabled, access to the entire memory array is permitted.
I I I I I nterrupts
or message center) is assigned to each port. The left port interrupt flag
(INT
Truth Table III — Example of Semaphore Procurement Sequence
NOTES:
1. This table denotes a sequence of events for only one of the eight semaphores on the IDT7025.
2. There are eight semaphore flags written to via I/O
3. CE = V
No Action
Left Port Writes "0" to Semaphore
Right Port Writes "0" to Semaphore
Left Port Writes "1" to Semaphore
Left Port Writes "0" to Semaphore
Right Port Writes "1" to Semaphore
Left Port Writes "1" to Semaphore
Right Port Writes "0" to Semaphore
Right Port Writes "1" to Semaphore
Left Port Writes "0" to Semaphore
Left Port Writes "1" to Semaphore
CE
IDT7025S/L
High-Speed 8K x 16 Dual-Port Static RAM
X
X
H
L
are push pull, not open drain outputs. On slaves the BUSY asserted internally inhibits write.
and enable inputs of this port. If t
when BUSY
The IDT7025 provides two ports with separate control, address and
If the user chooses the interrupt function, a memory location (mail box
L
L
) is asserted when the right port writes to memory location 1FFE
CE
IH
X
X
H
L
, SEM = V
R
Inputs
L
R
and BUSY
outputs are driving LOW regardless of actual logic level on the pin.
Functions
NO MATCH
A
A
MATCH
MATCH
MATCH
0R
0L
IL
, to access the semaphores. Refer to the Semaphore Read/Write Truth Table.
-A
-A
R
12L
12R
are both outputs when the part is configured as a master. BUSY are inputs when configured as a slave. BUSYx outputs on the IDT7025
APS
BUSY
is not met, either BUSY
(2)
H
H
H
L
Outputs
(1)
D
BUSY
0
0
- D
(2)
and read from all I/0's. These eight semaphores are addressed by A
H
H
H
L
1
1
1
1
1
1
1
0
0
0
0
15
R
outputs are driving LOW regardless of actual logic level on the pin. Writes to the right port are internally ignored
(1)
Left
L
Write Inhibit
or BUSY
Function
Normal
Normal
Normal
D
0
2683 tbl 17
R
- D
IH
= LOW will result. BUSY
).
15
(3)
1
1
1
1
1
1
1
1
0
0
0
6.42
Right
18
(HEX), where a write is defined as the CE
I. The left port clears the interrupt by an address location 1FFE access
when CE
interrupt flag (INT
1FFF (HEX) and to clear the interrupt flag (INT
the memory location 1FFF
user-defined, since it is an addressable SRAM location. If the interrupt
function is not used, address locations 1FFE and 1FFF are not used as
mail boxes, but as part of the random access memory. Refer to Truth Table
I for the interrupt operation.
Semaphore free
Left port has semaphore token
No change. Right side has no write access to semaphore
Right port obtains semaphore token
No change. Left port has no write access to semaphore
Left port obtains semaphore token
Semaphore free
Right port has semaphore token
Semaphore free
Left port has semaphore token
Semaphore free
Military, Industrial and Commercial Temperature Ranges
L
= OE
L
L
R
and BUSY
= V
) is asserted when the left port writes to memory location
IL
, R/W
R
,
outputs cannot be LOW simultaneously.
The message (16 bits) at 1FFE or 1FFF is
L
is a "don't care". Likewise, the right port
Status
0
- A
2
R
.
= R/W
R
), the right port must access
R
= V
IL
(1,2,3)
per Truth Table
2683 tbl 18