CY62148ELL-55SXIT Cypress Semiconductor Corp, CY62148ELL-55SXIT Datasheet - Page 6

• Manufacturer Part Number: CY62148ELL-55SXIT
• Description: IC SRAM 4MBIT 55NS 32SOIC
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY62148ELL-55SXIT

• Memory Size: 4M (512K x 8)
• Format - Memory: RAM
• Memory Type: SRAM
• Speed: 55ns
• Interface: Parallel
• Voltage - Supply: 4.5 V ~ 5.5 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 32-SOIC (11.30mm Width)
• Memory Configuration: 512K X 8
• Access Time: 55ns
• Supply Voltage Range: 4.5V To 5.5V
• Memory Case Style: SOIC
• No. Of Pins: 32
• Operating Temperature Range: -40°C To +85°C
• Rohs Compliant: Yes
• Density: 4Mb
• Access Time (max): 55ns
• Sync/async: Asynchronous
• Architecture: Not Required
• Clock Freq (max): Not RequiredMHz
• Operating Supply Voltage (typ): 5V
• Address Bus: 19b
• Package Type: SOIC
• Operating Temp Range: -40C to 85C
• Number Of Ports: 1
• Supply Current: 20mA
• Operating Supply Voltage (min): 4.5V
• Operating Supply Voltage (max): 5.5V
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 32
• Word Size: 8b
• Number Of Words: 512K
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

Switching Characteristics
Over the operating range
Document #: 38-05442 Rev. *H
Read Cycle
t
t
t
t
t
t
t
t
t
t
t
Write Cycle
t
t
t
t
t
t
t
t
t
t
Notes
RC
AA
OHA
ACE
DOE
LZOE
HZOE
LZCE
HZCE
PU
PD
WC
SCE
AW
HA
SA
PWE
SD
HD
HZWE
LZWE
14. Test conditions for all parameters other than tri-state parameters assume signal transition time of 3 ns or less, timing reference levels of 1.5 V, input pulse levels
15. SOIC package is available only in 55 ns speed bin.
16. At any temperature and voltage condition, t
17. t
18. The internal wre.ite time of the memory is defined by the overlap of WE, CE = V
Parameter
of 0 to 3 V, and output loading of the specified I
terminate a write by going INACTIVE. The data input setup and hold timing should be referenced to the edge of the signal that terminates the write.
HZOE
, t
V
HZCE
CE
CC
[18]
, and t
[14]
HZWE
Read cycle time
Address to data valid
Data hold from address change
CE LOW to data valid
OE LOW to data valid
OE LOW to low Z
OE HIGH to high Z
CE LOW to low Z
CE HIGH to high Z
CE LOW to power-up
CE HIGH to power-down
Write cycle time
CE LOW to write end
Address setup to write end
Address hold from write end
Address setup to write start
WE pulse width
Data setup to write end
Data hold from write end
WE LOW to high Z
WE HIGH to low Z
transitions are measured when the outputs enter a high impedance state.
Description
HZCE
V
OL
[16]
[16]
t
is less than t
CC(min)
[16]
CDR
[16, 17]
[16, 17]
[16, 17]
/I
OH
Figure 3. Data Retention Waveform
as shown in the
LZCE
, t
HZOE
“AC Test Loads and Waveforms”
DATA RETENTION MODE
is less than t
Min
45
10
10
45
35
35
35
25
10
–
–
–
5
–
–
0
–
0
0
0
–
IL
V
. All signals must be ACTIVE to initiate a write and any of these signals can
DR
45 ns
> 2.0 V
LZOE
, and t
Max
HZWE
45
45
22
18
18
45
18
–
–
–
–
–
–
–
–
–
–
–
–
–
is less than t
on page
5.
Min
LZWE
V
55
10
10
55
40
40
40
25
10
–
–
–
5
–
–
0
–
0
0
0
–
CC(min)
t
R
for any device.
55 ns
CY62148E MoBL
[15]
Max
55
55
25
20
20
55
20
–
–
–
–
–
–
–
–
–
–
–
–
–
–
Page 6 of 14
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
®
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