93LC86/P Microchip Technology, 93LC86/P Datasheet - Page 7

• Manufacturer Part Number: 93LC86/P
• Description: IC EEPROM 16KBIT 3MHZ 8DIP
• Manufacturer: Microchip Technology

Specifications of 93LC86/P

• Memory Size: 16K (2K x 8 or 1K x 16)
• Package / Case: 8-DIP (0.300", 7.62mm)
• Operating Temperature: 0°C ~ 70°C
• Format - Memory: EEPROMs - Serial
• Memory Type: EEPROM
• Speed: 2MHz, 3MHz
• Interface: Microwire, 3-Wire Serial
• Voltage - Supply: 2.5 V ~ 6.0 V
• Organization: 1 K x 16 or 2 K x 8
• Interface Type: Microwire
• Maximum Clock Frequency: 2 MHz
• Supply Voltage (max): 6 V
• Supply Voltage (min): 2.5 V
• Maximum Operating Current: 3 mA
• Maximum Operating Temperature: + 70 C
• Mounting Style: Through Hole
• Minimum Operating Temperature: 0 C
• Operating Supply Voltage: 2.5 V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

3.0
3.1
The READ instruction outputs the serial data of the
addressed memory location on the DO pin. A dummy
zero bit precedes the 16-bit (x16 organization) or 8-bit
(x8 organization) output string. The output data bits will
toggle on the rising edge of the CLK and are stable
after the specified time delay (T
possible when CS is held high and clock transitions
continue.
automatically increment and output data sequentially.
3.2
The ERASE instruction forces all data bits of the
specified address to the logical “1” state. The self-timed
programming cycle is initiated on the rising edge of
CLK as the last address bit (A0) is clocked in. At this
point, the CLK, CS and DI inputs become “don’t cares”.
The DO pin indicates the Ready/Busy status of the
device if the CS is high. The Ready/Busy status will be
displayed on the DO pin until the next Start bit is
received as long as CS is high. Bringing the CS low will
place the device in Standby mode and cause the DO
pin to enter the high-impedance state. DO at logical “0”
indicates that programming is still in progress. DO at
logical “1” indicates that the register at the specified
address has been erased and the device is ready for
another instruction.
The erase cycle takes 3 ms per word (typical).
3.3
The WRITE instruction is followed by 16 bits (or by 8
bits) of data to be written into the specified address.
The self-timed programming cycle is initiated on the
rising edge of CLK as the last data bit (D0) is clocked
in. At this point, the CLK, CS and DI inputs become
“don’t cares”.
The DO pin indicates the Ready/Busy status of the
device if the CS is high. The Ready/Busy status will be
displayed on the DO pin until the next Start bit is
received as long as CS is high. Bringing the CS low will
place the device in Standby mode and cause the DO
pin to enter the high-impedance state. DO at logical “0”
indicates that programming is still in progress. DO at
logical “1” indicates that the register at the specified
address has been written and the device is ready for
another instruction.
The write cycle takes 3 ms per word (typical).
 2010 Microchip Technology Inc.
DEVICE OPERATION
READ
ERASE
WRITE
The
memory
Address
PD
). Sequential read is
Pointer
will
3.4
The ERAL instruction will erase the entire memory array
to the logical “1” state. The ERAL cycle is identical to
the erase cycle except for the different opcode. The
ERAL cycle is completely self-timed and commences
on the rising edge of the last address bit (A0). Note that
the Least Significant 8 or 9 address bits are “don’t care”
bits, depending on selection of x16 or x8 mode. Clock-
ing of the CLK pin is not necessary after the device has
entered the self clocking mode. The ERAL instruction is
ensured at V
The DO pin indicates the Ready/Busy status of the
device if the CS is high. The Ready/Busy status will be
displayed on the DO pin until the next Start bit is
received as long as CS is high. Bringing the CS low will
place the device in Standby mode and cause the DO
pin to enter the high-impedance state. DO at logical “0”
indicates that programming is still in progress. DO at
logical “1” indicates that the entire device has been
erased and is ready for another instruction.
The ERAL cycle takes 15 ms maximum (8 ms typical).
3.5
The WRAL instruction will write the entire memory array
with the data specified in the command. The WRAL
cycle is completely self-timed and commences on the
rising edge of the last address bit (A0). Note that the
Least Significant 8 or 9 address bits are “don’t cares”,
depending on selection of x16 or x8 mode. Clocking of
the CLK pin is not necessary after the device has
entered the self clocking mode. The WRAL command
does include an automatic ERAL cycle for the device.
Therefore, the WRAL instruction does not require an
ERAL instruction but the chip must be in the EWEN
status. The WRAL instruction is ensured at Vcc = +4.5V
to +6.0V.
The DO pin indicates the Ready/Busy status of the
device if the CS is high. The Ready/Busy status will be
displayed on the DO pin until the next Start bit is
received as long as CS is high. Bringing the CS low will
place the device in Standby mode and cause the DO
pin to enter the high-impedance state. DO at logical “0”
indicates that programming is still in progress. DO at
logical “1” indicates that the entire device has been
written and is ready for another instruction.
The WRAL cycle takes 30 ms maximum (16 ms
typical).
Erase All (ERAL)
Write All (WRAL)
CC
= +4.5V to +6.0V.
93LC76/86
DS21131F-page 7