25AA160/SN Microchip Technology, 25AA160/SN Datasheet - Page 10

• Manufacturer Part Number: 25AA160/SN
• Description: IC EEPROM 16KBIT 1MHZ 8SOIC
• Manufacturer: Microchip Technology

Specifications of 25AA160/SN

• Format - Memory: EEPROMs - Serial
• Memory Type: EEPROM
• Memory Size: 16K (2K x 8)
• Speed: 1MHz
• Interface: SPI, 3-Wire Serial
• Voltage - Supply: 1.8 V ~ 5.5 V
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 8-SOIC (3.9mm Width)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

25AA160/25LC160/25C160
3.5
The Read Status Register (RDSR) instruction provides
access to the Status register. The Status register may
be read at any time, even during a write cycle. The
Status register is formatted as follows:
The Write-In-Process (WIP) bit indicates whether the
25XX160 is busy with a write operation. When set to a
‘
in progress. This bit is read-only.
FIGURE 3-6:
3.6
The Write Status register (WRSR) instruction allows the
user to select one of four levels of protection for the
array by writing to the appropriate bits in the Status
register. The array is divided up into four segments.
The user has the ability to write-protect none, one, two
or all four of the segments of the array. The partitioning
is controlled as shown in Table 3-2.
The Write-Protect Enable (WPEN) bit is a nonvolatile
bit that is available as an enable bit for the WP pin. The
Write-Protect (WP) pin and the Write-Protect Enable
(WPEN) bit in the Status register control the program-
mable hardware write-protect feature. Hardware write
protection is enabled when WP pin is low and the
WPEN bit is high. Hardware write protection is disabled
when either the WP pin is high or the WPEN bit is low.
When the chip is hardware write-protected, only writes
to nonvolatile bits in the Status register are disabled.
See Table 3-3 for a matrix of functionality on the WPEN
bit.
See Figure 3-7 for the WRSR timing sequence.
DS21231D-page 10
1
WPEN
’, a write is in progress, when set to a ‘
SCK
7
CS
SO
SI
Read Status Register (RDSR)
Write Status Register (WRSR)
X
6
5
X
0
0
X
4
READ STATUS REGISTER TIMING SEQUENCE
0
1
BP1
High-impedance
3
0
2
instruction
BP0
2
0
3
0
WEL
0
4
1
’, no write is
1
5
WIP
0
0
6
1
7
The Write Enable Latch (WEL) bit indicates the status
of the write enable latch. When set to a ‘
allows writes to the array, when set to a ‘
prohibits writes to the array. The state of this bit can
always be updated via the WREN or WRDI commands
regardless of the state of write protection on the Status
register. This bit is read-only.
The Block Protection (BP0 and BP1) bits indicate
which blocks are currently write-protected. These bits
are set by the user issuing the WRSR instruction. These
bits are nonvolatile.
See Figure 3-6 for the RDSR timing sequence.
TABLE 3-2:
7
8
BP1
6
0
0
1
1
9
data from Status register
10
5
11
4
ARRAY PROTECTION
BP0
0
1
0
1
12
3
 2004 Microchip Technology Inc.
13
2
Array Addresses
Write-Protected
(0600h - 07FFh)
(0400h - 07FFh)
(0000h - 07FFh)
14
1
upper 1/4
upper 1/2
none
all
15
0
1
0
’, the latch
’, the latch