ST62T32BQ6 STMicroelectronics, ST62T32BQ6 Datasheet
ST62T32BQ6
Specifications of ST62T32BQ6
Related parts for ST62T32BQ6
ST62T32BQ6 Summary of contents
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OTP/EPROM MCUs WITH A/D CONVERTER, 16-BIT AUTO-RELOAD TIMER, EEPROM, SPI AND UART 3.0 to 6.0V Supply Operating Range 8 MHz Maximum Clock Frequency -40 to +125°C Operating Temperature Range Run, Wait and Stop Modes 5 Interrupt Vectors Look-up Table ...
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ST62T32B ST62E32B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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ORDERING INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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GENERAL DESCRIPTION 1.1 INTRODUCTION The ST62T32B and ST62E32B devices are low cost members of the ST62xx 8-bit HCMOS family of microcontrollers, which is targeted at low to me- dium complexity applications. All ST62xx devices are based on a building ...
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ST62T32B ST62E32B INTRODUCTION (Cont’d) OTP and EPROM devices are functionally identi- cal. The ROM based versions offer the same func- tionality selecting as ROM options the options de- fined in the programmable option byte of the OTP/EPROM versions.OTP devices offer ...
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PIN DESCRIPTIONS V and V . Power is supplied to the MCU via DD SS these two pins the power connection and the ground connection. SS and V . Power is supplied to the ...
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ST62T32B ST62E32B 1.3 MEMORY MAP 1.3.1 Introduction The MCU operates in three separate memory spaces: Program space, Data space, and Stack space. Operation in these three memory spaces is described in the following paragraphs. Briefly, Program space contains user program ...
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... U.V. erasure that also results into the whole EPROM context erasure. Note: Once the Readout Protection is activated longer possible, even for STMicroelectronics, to gain access to the Program memory contents. Returned parts with a protection set can therefore not be accepted. ...
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ST62T32B ST62E32B MEMORY MAP (Cont’d) 1.3.3 Data Space Data Space accommodates all the data necessary for processing the user program. This space com- prises the RAM resource, the processor core and peripheral registers, as well as read-only data such as ...
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MEMORY MAP (Cont’d) 1.3.5 Data Window Register (DWR) The Data read-only memory window is located from address 0040h to address 007Fh in Data space. It allows direct reading of 64 consecutive bytes locat- ed anywhere in program memory, between ad- ...
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ST62T32B ST62E32B MEMORY MAP (Cont’d) 1.3.6 Data RAM/EEPROM (DRBR) Address: CBh — Write only DRBR4 DRBR3 Bit 7-5 = These bits are not used Bit 4 - DRBR4. This bit, when set, selects RAM Page 2. ...
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MEMORY MAP (Cont’d) 1.3.7 EEPROM Description EEPROM memory is located in 64-byte pages in data space. This memory may be used by the user program for non-volatile data storage. Data space from 00h to 3Fh is paged as described in ...
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ST62T32B ST62E32B MEMORY MAP (Cont’d) Additional Notes on Parallel Mode: If the user wishes to perform parallel program- ming, the first step should be to set the E2PAR2 bit. From this time on, the EEPROM will be ad- dressed in ...
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... EEPROM data pages are supplied in the virgin state FFh. Partial or total programming of EEP- ROM data memory can be performed either through the application software, or through an ex- ternal programmer. Any STMicroelectronics tool used for the program memory (OTP/EPROM) can also be used to program the EEPROM data mem- ory. ...
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ST62T32B ST62E32B 2 CENTRAL PROCESSING UNIT 2.1 INTRODUCTION The CPU Core of ST6 devices is independent of the I/O or Memory configuration. As such, it may be thought independent central processor communicating with on-chip I/O, Memory and ...
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CPU REGISTERS (Cont’d) However, if the program space contains more than 4096 bytes, the additional memory in program space can be addressed by using the Program Bank Switch register. The PC value is incremented after reading the ad- dress of ...
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ST62T32B ST62E32B 3 CLOCKS, RESET, INTERRUPTS AND POWER SAVING MODES 3.1 CLOCK SYSTEM The MCU features a Main Oscillator which can be driven by an external clock, or used in conjunction with an AT-cut parallel resonant crystal or a suita- ...
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CLOCK SYSTEM (Cont’d) Turning on the main oscillator is achieved by re- setting the OSCOFF bit of the OSCR Register or by resetting the MCU. Restarting the main oscilla- tor implies a delay comprising the oscillator start up delay period ...
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ST62T32B ST62E32B CLOCK SYSTEM (Cont’d) Figure 10. OSG Filtering Principle (1) (2) (3) (4) (1) Maximum Frequency for the device to work correctly (2) Actual Quartz Crystal Frequency at OSCin pin (3) Noise from OSCin (4) Resulting Internal Frequency Figure ...
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CLOCK SYSTEM (Cont’d) Figure 12. Clock Circuit Block Diagram MAIN OSCILLATOR Figure 13. Maximum Operating Frequency (f Maximum FREQUENCY (MHz 2.5 3 Notes this area, operation is guaranteed at the ...
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ST62T32B ST62E32B 3.2 RESETS The MCU can be reset in three ways: – by the external Reset input being pulled low; – by Power-on Reset; – by the digital Watchdog peripheral timing out. 3.2.1 RESET Input The RESET pin may ...
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RESETS (Cont’d) 3.2.3 Watchdog Reset The MCU provides a Watchdog timer function in order to ensure graceful recovery from software upsets. If the Watchdog register is not refreshed before an end-of-count condition is reached, the internal reset will be activated. ...
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ST62T32B ST62E32B RESETS (Cont’d) Table 7. Register Reset Status Register Oscillator Control Register EEPROM Control Register Port Data Registers Port Direction Register Port Option Register Interrupt Option Register TIMER Status/Control AR TIMER Status/Control 1 Register AR TIMER Status/Control 2 Register ...
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DIGITAL WATCHDOG The digital Watchdog consists of a reloadable downcounter timer which can be used to provide controlled recovery from software upsets. The Watchdog circuit generates a Reset when the downcounter reaches zero. User software can prevent this reset ...
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ST62T32B ST62E32B DIGITAL WATCHDOG (Cont’d) The Watchdog is associated with a Data space register (Digital WatchDog Register, DWDR, loca- tion 0D8h) which is described in greater detail in Section 3.3.1 Digital Watchdog Register This register is set to 0FEh on ...
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DIGITAL WATCHDOG (Cont’d) 3.3.1 Digital Watchdog Register (DWDR) Address: 0D8h — Read/Write Reset status: 1111 1110 Bit Watchdog Control bit If the hardware option is selected, this bit is forced ...
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ST62T32B ST62E32B DIGITAL WATCHDOG (Cont’d) These instructions test the C bit and Reset the MCU (i.e. disable the Watchdog) if the bit is set (i.e. if the Watchdog is active), thus disabling the Watchdog. In all modes, a minimum of ...
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INTERRUPTS The CPU can manage four Maskable Interrupt sources, in addition to a Non Maskable Interrupt source (top priority interrupt). Each source is asso- ciated with a specific Interrupt Vector which con- tains a Jump instruction to the associated ...
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ST62T32B ST62E32B INTERRUPTS (Cont’d) 3.4.2 Interrupt Procedure The interrupt procedure is very similar to a call pro- cedure, indeed the user can consider the interrupt as an asynchronous call procedure. As this is an asynchronous event, the user cannot know ...
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INTERRUPTS (Cont’d) 3.4.3 Interrupt Option Register (IOR) The Interrupt Option Register (IOR) is used to en- able/disable the individual interrupt sources and to select the operating mode of the external interrupt inputs. This register is write-only and cannot be accessed ...
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ST62T32B ST62E32B IINTERRUPTS (Cont’d) Interrupt Polarity Register (IPR) Address: DAh — Read/Write PortE PortD PortC PortA PortB In conjunction with IOR register ESB bit, the polar- ity of I/O pins triggered interrupts can be selected by ...
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INTERRUPTS (Cont’d) Figure 21. Interrupt Block Diagram FROM REGISTER PORT A,B,C,D,E SINGLE BIT ENABLE PBE V DD PORT C Bits NMI IPR Bit 0 PORT A PBE Bits IPR Bit 4 PORT E PBE Bits IPR Bit 1 PBE PORT ...
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ST62T32B ST62E32B 3.5 POWER SAVING MODES The WAIT and STOP modes have been imple- mented in the ST62xx family of MCUs in order to reduce the product’s electrical consumption during idle periods. These two power saving modes are described in ...
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POWER SAVING MODE (Cont’d) 3.5.3 Exit from WAIT and STOP Modes The following paragraphs describe how the MCU exits from WAIT and STOP modes, when an inter- rupt occurs (not a Reset). It should be noted that the restart sequence ...
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ST62T32B ST62E32B 4 ON-CHIP PERIPHERALS 4.1 I/O PORTS The MCU features Input/Output lines which may be individually programmed as any of the following input or output configurations: – Input without pull-up or interrupt – Input with pull-up and interrupt – ...
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I/O PORTS (Cont’d) 4.1.1 Operating Modes Each pin may be individually programmed as input or output with various configurations. This is achieved by writing the relevant bit in the Data (DR), Data Direction (DDR) and Option reg- isters (OR). Table ...
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ST62T32B ST62E32B I/O PORTS (Cont’d) 4.1.2 Safe I/O State Switching Sequence Switching the I/O ports from one state to another should be done in a sequence which ensures that no unwanted side effects can occur. The recom- mended safe transitions ...
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I/O PORTS (Cont’d) Table 14. I/O Port configuration for the ST62T32B/E32B MODE AVAILABLE ON PA0-PA7 PB0, PB3-PB7 Input PC5-PC7 (Reset state if PORT PULL option disabled) PD0-PD7 PE0-PE4 PA0-PA7 Input PB0, PB3-PB7 with pull up PC5-PC7 (Reset state if PORT ...
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ST62T32B ST62E32B I/O PORTS (Cont’d) 4.1.3 ARTimer alternate functions As long as PWMEN (resp. OVFEN) bit is kept low, the PA3/PWM (resp. PA2/OVF) pin is used as standard I/O pin and therefore can be configured in any mode through the ...
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I/O PORTS (Cont’d) Figure 24. Peripheral Interface Configuration of SPI, UART and AR Timer16 PD4/RXD1 PD5/TXD1 PD3/Sout PD2/Sin PD1/Scl PA3/PWM PA4/CP1 PA5/CP2 PA2/OVF V DD PID DR PID 0 MUX 1 PID PP/OD OPR 1 DR MUX 0 PID DR ...
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ST62T32B ST62E32B I/O PORTS (Cont’d) 4.1.6 I/O Port Option Registers ORA/B/C/D/E (CCh PA, CDh PB, CEh PC, CFh PD, FEh PE) Read/Write 7 Px7 Px6 Px5 Px4 Px3 Bit 7-0 = Px7 - Px0: Port and ...
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TIMER The MCU features an on-chip Timer peripheral, consisting of an 8-bit counter with a 7-bit program- mable prescaler, giving a maximum count of 2 The peripheral may be configured in three different operating modes. Figure 25 shows the ...
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ST62T32B ST62E32B TIMER (Cont’d) 4.2.1 Timer Operating Modes There are three operating modes, which are se- lected by the TOUT and DOUT bits (see TSCR register). These three modes correspond to the two clocks which can be connected to the ...
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TIMER (Cont’d) 4.2.3 Application Notes TMZ is set when the counter reaches zero; howev- er, it may also be set by writing 00h in the TCR register or by setting bit 7 of the TSCR register. The TMZ bit must ...
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ST62T32B ST62E32B 4.3 ARTIMER 16 The ARTIMER16 is a timer module based bit downcounter with Reload, Capture and Com- pare features to manage timing requirements. Two outputs provide PWM and Overflow (OVF) output signals each with programmable ...
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The maximum time for downcounting is therefore Psc x Tclk where Psc is the prescaler ratio, and Tclk the period of the main oscillator. This down counter is stopped and its content kept cleared as long as ...
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ST62T32B ST62E32B CENTRAL COUNTER (Cont’d) 4.3.1.3 Capture functions Content of the counter CT can always be down- loaded (captured) into the CP register at selecta- ble event occurrence on pins CP1 and CP2, while capture in RLCP is possible only ...
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Figure 29. Mask Impact on the Compare Functions in PWM mode (PWMD=0, PWMPOL=1) Counter Bit 0...3 MASK 000Fh 0007h 0003&000C = 0000h 0003h 0001h CMP = 000Fh 0003&0007 = ...
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ST62T32B ST62E32B 4.3.3 TIMINGS MEASUREMENT MODES These modes are based on the capture of the down counter content into either CP or RLCP reg- isters. Some are used in conjunction with a syn- chronisation of the down counter by reload ...
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TIMINGS MEASUREMENT MODES (Cont’d) CP2 triggered restart mode with CP2 event de- tection. This mode is enabled for RLDSEL2=1 and RLDSEL1=0. As long as RUNRES bit is set, an external event on CP2 pin generates both, at first the capture ...
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ST62T32B ST62E32B TIMINGS MEASUREMENT MODES (Cont’d) 4.3.3.2 Timing measurement without startup control The down counter is in free running mode with RUNRES bit set and RELOAD bit cleared. This means counter automatically restarts from FFFFh on zero overflow and signal ...
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CONTROL REGISTERS Status Control Register 1 (SCR1) Address: E8h - Read/Write/Clear only 7 RE- RUN- PSC2 PSC1 OVFIEN OVFFLG OVFMD LOAD RES Bits 7 & PSC2..PSC1. Clock Prescaler . These bits define the prescaler options for the ...
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ST62T32B ST62E32B CONTROL REGISTERS (Cont’d) Status Control Register 3 (SCR3) Address: E2h - Read/Write/Clear only 7 CP2PO CP2IE CP2FL CMPI- CMFLG Bit 7 = CP2POL. CP2 Edge Polarity Select . CP2POL defines the polarity for triggering ...
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CONTROL REGISTERS (Cont’d) Status Control Register 4 (SCR4) Address: E3h - Read/Write/Clear only 7 OVFP Res. Res. Res. Res. OL Bit7- Bit4 = Reserved, set to 0. Bit 3 = OVFPOL. Overflow Output Polarity . This bit defines the polarity ...
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ST62T32B ST62E32B Reload/Capture Register High Byte (RLCP) Address: E9h - Read/ (Write if RELOAD bit set) D7-D0. These bits are the High byte (D15-D8) of the 16-bit Reload/Capture Register. Reload/Capture Register Low Byte (RLCP) Address: EAh - Read/ (Write if ...
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A/D CONVERTER (ADC) The A/D converter peripheral is an 8-bit analog to digital converter with analog inputs as alternate I/O functions (the number of which is device depend- ent), offering 8-bit resolution with a selectable con- version time of ...
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ST62T32B ST62E32B A/D CONVERTER (Cont’d) Since the ADC is on the same chip as the micro- processor, the user should not switch heavily load- ed output signals during conversion, if high preci- sion is required. Such switching will affect the ...
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(Universal Asynchronous Receiver/Transmitter) The UART provides the basic hardware for asyn- chronous serial communication which, combined with an appropriate software routine, gives a serial interface providing communication with common baud rates (up to 38,400 Baud ...
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ST62T32B ST62E32B 4.5.2 CLOCK GENERATION The UART contains a built-in divider of the MCU internal clock for most common Baud Rates as shown in Table 20. Other baud rate values can be calculated from the chosen oscillator frequency di- vided ...
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DATA RECEPTION The UART continuously looks for a falling edge on the input pin whenever a transmission is not ac- tive. Once an edge is detected it waits 1 bit time (8 states) to accommodate the Start bit, and ...
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ST62T32B ST62E32B REGISTERS (Cont’d) UART Control Register (UARTCR) Address: D7h, Read/Write 7 RXRDY TXMT RXIEN TXIEN BR2 Bit 7 = RXRDY. Receiver Ready . This flag be- comes active as soon as a complete byte has been received and copied ...
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SERIAL PERIPHERAL INTERFACE (SPI) The on-chip SPI is an optimized serial synchro- nous interface that supports a wide range of indus- try standard SPI specifications. The on-chip SPI is controlled by small and simple user software to perform serial ...
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ST62T32B ST62E32B SERIAL PERIPHERAL INTERFACE (Cont’d) After 8 clock pulses (D7..D0) the output Q4 of the 4-bit binary counter becomes low, disabling the clock from the counter and the data/shift register. Q4 enables the clock to generate an interrupt on ...
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SOFTWARE 5.1 ST6 ARCHITECTURE The ST6 software has been designed to fully use the hardware in the most efficient way possible while keeping byte usage to a minimum; in short, to provide byte efficient programming capability. The ST6 core ...
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ST62T32B ST62E32B 5.3 INSTRUCTION SET The ST6 core offers a set of 40 basic instructions which, when combined with nine addressing modes, yield 244 usable opcodes. They can be di- vided into six different types: load/store, arithme- tic/logic, conditional branch, ...
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INSTRUCTION SET (Cont’d) Arithmetic and Logic. These instructions are used to perform the arithmetic calculations and logic operations. In AND, ADD, CP, SUB instruc- tions one operand is always the accumulator while the other can be either a data space ...
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ST62T32B ST62E32B INSTRUCTION SET (Cont’d) Conditional Branch. The branch instructions achieve a branch in the program when the select- ed condition is met. Bit Manipulation Instructions. These instruc- tions can handle any bit in data space memory. One group either ...
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Opcode Map Summary. The following table contains an opcode map for the instructions used by the ST6 LOW 0 1 0000 0001 HI 2 JRNZ 4 CALL abc 0000 1 pcr 2 ext 1 2 JRNZ 4 ...
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ST62T32B ST62E32B Opcode Map Summary (Continued) LOW 8 9 1000 1001 HI 2 JRNZ abc 0000 1 pcr 2 ext 1 2 JRNZ abc 0001 1 pcr 2 ext 1 ...
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ELECTRICAL CHARACTERISTICS 6.1 ABSOLUTE MAXIMUM RATINGS This product contains devices to protect the inputs against damage due to high static voltages, how- ever it is advisable to take normal precaution to avoid application of any voltage higher than the ...
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ST62T32B ST62E32B 6.2 RECOMMENDED OPERATING CONDITIONS Symbol Parameter T Operating Temperature A V Operating Supply Voltage Oscillator Frequency OSC Internal Frequency with OSG f 2) OSG enable I Pin Injection Current (positive) INJ+ I Pin Injection Current ...
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DC ELECTRICAL CHARACTERISTICS (T = -40 to +125°C unless otherwise specified) A Symbol Parameter V Input Low Level Voltage IL All Input pins V Input High Level Voltage IH All Input pins (1) Hysteresis Voltage V Hys All Input ...
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ST62T32B ST62E32B 6.4 AC ELECTRICAL CHARACTERISTICS (T = -40 to +125°C unless otherwise specified) A Symbol Parameter t Supply Recovery Time REC Minimum Pulse Width (V T RESET pin WR NMI pin T EEPROM Write Time WEE Endurance EEPROM WRITE/ERASE ...
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TIMER CHARACTERISTICS (T = -40 to +125°C unless otherwise specified) A Symbol Parameter f Input Frequency on TIMER Pin IN t Pulse Width at TIMER Pin W 6.7 SPI CHARACTERISTICS (T = -40 to +125°C unless otherwise specified) A ...
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ST62T32B ST62E32B 7 GENERAL INFORMATION 7.1 PACKAGE MECHANICAL DATA Figure 41. 42-Pin Plastic Dual In-Line Package, Shrink 600-mil Width b2 D Figure 42. 52-Pin Plastic Quad Flat Package 76/ ...
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PACKAGE MECHANICAL DATA (Cont’d) Figure 43. 42-Pin Ceramic Shrink Dual-In-Line Package THERMAL CHARACTERISTIC Symbol Parameter RthJA Thermal Resistance CDIP42SW Test Conditions Min. SDIP42 QFP52 ST62T32B ST62E32B mm inches Dim. Min Typ Max Min Typ A 4.01 0.158 A1 0.76 0.030 ...
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... ST62T32B ST62E32B 7.2 ORDERING INFORMATION Table 27. OTP/EPROM VERSION ORDERING INFORMATION Sales Type Memory (Bytes) ST62E32BF1 ST62T32BB6 ST62T32BB3 ST62T32BQ6 ST62T32BQ3 7.3 IMPORTANT NOTE For OTP devices, data retention and programmability must be guaranteed by a screening procedure. Re- fer to Application Note AN886. 78/83 Program I/O 7948 (EPROM) 30 7948 (OTP) ...
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AUTO-RELOAD TIMER, EEPROM, SPI AND UART 3.0 to 6.0V Supply Operating Range 8 MHz Maximum Clock Frequency -40 to +125°C Operating Temperature Range Run, Wait and Stop Modes 5 Interrupt Vectors Look-up Table capability in Program Memory Data ...
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ST6232B 1GENERAL DESCRIPTION 1.1 INTRODUCTION The ST6232B is mask programmed ROM version of ST62T32B OTP devices. They offer the same functionality as OTP devices, selecting as ROM options the options defined in the programmable option byte of the OTP version. ...
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... This listing refers exactly to the mask which will be used to produce the specified MCU. The listing is then returned to the customer who must thoroughly check, complete, sign and return it to STMicroelectronics. The signed listing forms a Table 2. ROM version Ordering Information Sales Type ST6232BB1/XXX ...
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... Software Activation [ ] Hardware Activation [ ] Enabled [ ] Disabled [ ] Enabled [ ] Disabled [ ] Enabled Fuse is blown by STMicroelectronics [ ] Fuse can be blown by the customer [ ] Disabled [ ] Enabled [ ] Disabled [ ] Enabled [ ] Disabled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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... No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics ...