IDT70V9269S12PRFI IDT, Integrated Device Technology Inc, IDT70V9269S12PRFI Datasheet - Page 9

• Manufacturer Part Number: IDT70V9269S12PRFI
• Description: IC SRAM 256KBIT 12NS 128TQFP
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of IDT70V9269S12PRFI

• Format - Memory: RAM
• Memory Type: SRAM - Dual Port, Synchronous
• Memory Size: 256K (16K x 16)
• Speed: 12ns
• Interface: Parallel
• Voltage - Supply: 3 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 128-TQFP, 128-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 70V9269S12PRFI; 800-1399

AC Electrical Characteristics Over the Operating Temperature Range
(Read and Write Cycle Timing)
NOTES:
1. Transition is measured 0mV from Low or High-impedance voltage with the Output Test Load (Figure 2). This parameter is guaranteed by device characteriza-
2. The Pipelined output parameters (t
3. All input signals are synchronous with respect to the clock except for the asynchronous Output Enable (OE) and FT/PIPE. FT/PIPE should be treated as a
4. 'X' in part number indicates power rating (S or L).
Port-to-Port Delay
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
CYC1
CYC2
CH1
CL1
CH2
CL2
R
F
SA
HA
SC
HC
SW
HW
SD
HD
SAD
HAD
SCN
HCN
SRST
HRST
OE
OLZ
OHZ
CD1
CD2
DC
CKHZ
CKLZ
CWDD
CCS
IDT70V9279/69S/L
High-Speed 32/16K x 16 Dual-Port Synchronous Static RAM
tion, but is not production tested.
FT/PIPE = V
DC signal, i.e. steady state during operation.
Symbol
IL
Clock Cycle Time (Flow-Through)
Clock Cycle Time (Pipelined)
Clock High Time (Flow-Through)
Clock Low Time (Flow-Through)
Clock High Time (Pipelined)
Clock Low Time (Pipelined)
Clock Rise Time
Clock Fall Time
Chip Enable Setup Time
Chip Enable Hold Time
R/W Setup Time
R/W Hold Time
Input Data Setup Time
Input Data Hold Time
Output Enable to Data Valid
Output Enable to Output Low-Z
Output Enable to Output High-Z
Clock to Data Valid (Flow-Through)
Clock to Data Valid (Pipelined)
Data Output Hold After Clock High
Clock High to Output High-Z
Clock High to Output Low-Z
Clock-to-Clock Setup Time
Address Setup Time
Address Hold Time
ADS Setup Time
ADS Hold Time
CNTEN Setup Time
CNTEN Hold Time
CNTRST Setup Time
CNTRST Hold Time
Write Port Clock High to Read Data Delay
for that port.
CYC2
, t
CD2
(1)
(2)
(1)
) apply to either or both left and right ports when FT/PIPE = V
(2)
(2)
(1)
(2)
(1)
(2)
(2)
(2)
Parameter
(2)
(3,4)
(V
6.42
DD
9
= 3.3V ± 0.3V, T
Industrial and Commercial Temperature Ranges
70V9279/69X12
Min.
____
____
____
____
____
____
____
30
20
12
12
Com'l Only
8
8
4
4
4
4
4
4
4
2
2
2
2
1
1
1
1
1
1
1
1
IH
. Flow-through parameters (t
A
= 0°C to +70°C)(Cont'd)
Max.
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____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
12
25
12
40
15
3
3
7
9
70V9279/69X15
Min.
____
____
____
____
____
____
____
35
25
12
12
10
10
Com'l Only
4
4
4
4
4
4
4
2
2
2
2
1
1
1
1
1
1
1
1
Max.
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____
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____
____
30
50
20
15
15
CYC1
3
3
7
9
, t
3743 tbl 11b
CD1
Unit
) apply when
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns