CY7C025-25AXI Cypress Semiconductor Corp, CY7C025-25AXI Datasheet - Page 4

• Manufacturer Part Number: CY7C025-25AXI
• Description: IC SRAM 128KBIT 25NS 100LQFP
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY7C025-25AXI

• Format - Memory: RAM
• Memory Type: SRAM - Dual Port, Asynchronous
• Memory Size: 128K (8K x 16)
• Speed: 25ns
• Interface: Parallel
• Voltage - Supply: 4.5 V ~ 5.5 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Selection Guide
Architecture
The CY7C024/024A/0241 and CY7C025/0251 consist of an
array of 4K words of 16/18 bits each and 8K words of 16/18 bits
each of dual-port RAM cells, I/O and address lines, and control
signals (CE, OE, R/W). These control pins permit independent
access for reads or writes to any location in memory. To handle
simultaneous writes/reads to the same location, a BUSY pin is
provided on each port. Two interrupt (INT) pins can be used for
port-to-port communication. Two semaphore (SEM) control pins
are used for allocating shared resources. With the M/S pin, the
CY7C024/024A/0241 and CY7C025/0251 can function as a
master (BUSY pins are outputs) or as a slave (BUSY pins are
inputs). The CY7C024/024A/0241 and CY7C025/0251 have an
automatic power down feature controlled by CE. Each port is
provided with its own output enable control (OE), which allows
data to be read from the device.
Functional Description
Write Operation
Data must be set up for a duration of t
of R/W to guarantee a valid write. A write operation is controlled
by either the R/W pin (see
Required inputs for non contention operations are summarized
in
If a location is being written to by one port and the opposite port
attempts to read that location, a port-to-port flowthrough delay
must occur before the data is read on the output; otherwise the
data read is not deterministic. Data is valid on the port t
the data is presented on the other port.
Read Operation
When reading the device, the user must assert both the OE and
CE pins. Data is available t
asserted.
CY7C025/0251 wishes to access a semaphore flag, then the
SEM pin must be asserted instead of the CE pin, and OE must
also be asserted.
Interrupts
The upper two memory locations may be used for message
passing.
CY7C024/024A/0241, 1FFF for the CY7C025/0251) is the
mailbox for the right port and the second-highest memory
location (FFE for the CY7C024/024A/0241, 1FFE for the
CY7C025/0251) is the mailbox for the left port. When one port
writes to the other port’s mailbox, an interrupt is generated to the
owner. The interrupt is reset when the owner reads the contents
of the mailbox. The message is user defined.
Document #: 38-06035 Rev. *D
Maximum Access Time (ns)
Typical Operating Current (mA)
Typical Standby Current for I
Table
1.
The
If
the
Parameter
highest
user
Figure
memory
of
SB1
ACE
the
(mA)
7) or the CE pin (see
after CE or t
CY7C024/024A/0241
location
SD
before the rising edge
7C024/024A/0241–15
DOE
(FFF
7C025/0251–15
after OE is
Figure
DDD
190
for
15
50
after
the
8).
or
Each port can read the other port’s mailbox without resetting the
interrupt. The active state of the BUSY signal (to a port) prevents
the port from setting the interrupt to the winning port. Also, an
active BUSY to a port prevents that port from reading its own
mailbox and thus resetting the interrupt to it.
If your application does not require message passing, do not
connect the interrupt pin to the processor’s interrupt request
input pin.
The operation of the interrupts and their interaction with Busy are
summarized in
Busy
The CY7C024/024A/0241 and CY7C025/0251 provide on-chip
arbitration to resolve simultaneous memory location access
(contention). If both ports’ CEs are asserted and an address
match occurs within t
which port has access. If t
permission to the location, but which one is not predictable.
BUSY is asserted t
is taken LOW.
Master/Slave
A M/S pin is provided to expand the word width by configuring
the device as either a master or a slave. The BUSY output of the
master is connected to the BUSY input of the slave. This allows
the device to interface to a master device with no external
components. Writing to slave devices must be delayed until after
the BUSY input has settled (t
chip may begin a write cycle during a contention situation. When
tied HIGH, the M/S pin allows the device to be used as a master
and, therefore, the BUSY line is an output. BUSY can then be
used to send the arbitration outcome to a slave.
Semaphore Operation
The CY7C024/024A/0241 and CY7C025/0251 provide eight
semaphore latches, which are separate from the dual-port
memory locations. Semaphores are used to reserve resources
that are shared between the two ports. The state of the
semaphore indicates that a resource is in use. For example, if
the left port wants to request a given resource, it sets a latch by
writing a zero to a semaphore location. The left port then verifies
its success in setting the latch by reading it. After writing to the
semaphore, SEM or OE must be deasserted for tSOP before
attempting to read the semaphore. The semaphore value is
available t
write. If the left port was successful (reads a zero), it assumes
control of the shared resource, otherwise (reads a one) it
assumes the right port has control and continues to poll the
semaphore. When the right side has relinquished control of the
semaphore (by writing a one), the left side succeeds in gaining
control of the semaphore. If the left side no longer requires the
semaphore, a one is written to cancel its request.
7C024/0241–25
7C025/0251–25
170
25
40
SWRD
Table 2
+ t
DOE
BLA
PS
7C024/0241–35
7C025/0251–35
on page 5.
after an address match or t
of each other, the busy logic determines
after the rising edge of the semaphore
PS
160
35
30
is violated, one port definitely gains
CY7C024/024A/0241
BLC
or t
BLA
CY7C025/0251
). Otherwise, the slave
7C024/0241–55
7C025/0251–55
150
55
20
Page 4 of 21
BLC
after CE
[+] Feedback