AT26F004-MU Atmel, AT26F004-MU Datasheet
AT26F004-MU
Specifications of AT26F004-MU
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AT26F004-MU Summary of contents
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... SOIC (150-mil and 208-mil wide) – 8-pad MLF ( 1.00 mm) 1. Description The AT26F004 is a serial interface Flash memory device designed for use in a wide variety of high-volume consumer based applications in which program code is shad- owed from Flash memory into embedded or external RAM for execution. The flexible ...
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... Specifically designed for use in 3-volt systems, the AT26F004 supports read, program, and erase operations with a supply voltage range of 2.7V to 3.6V. No separate voltage is required for programming and erasing ...
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... HOLD 4. Memory Array To provide the greatest flexibility, the memory array of the AT26F004 can be erased in four lev- els of granularity including a full chip erase. In addition, the array has been divided into physical sectors of various sizes, of which each sector can be individually protected from program and erase operations ...
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... Figure 4-1. Internal Sectoring for Sector Protection AT26F004 4 Memory Architecture Diagram 64KB Block Erase Function (D8h Command) (52h Command) (20h Command) 16KB (Sector 10) 8KB (Sector 9) 8KB (Sector 8) 64KB 32KB (Sector 7) 64KB 64KB (Sector 6) 64KB 64KB (Sector 0) Block Erase Detail 32KB 4KB ...
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... SPI Master. All opcode, address, and data bytes are transferred with the most significant bit (MSB) first. An operation is ended by deasserting the CS pin. Opcodes not supported by the AT26F004 will be ignored by the device and no operation will be started. The device will continue to ignore any data presented on the SI pin until the start of the next operation (CS pin being deasserted and then reasserted) ...
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... Three address bytes are only required for the first operation to designate the address at which to start the programming. Afterwards, the internal address counter automatically increments, so subsequent Sequential Program Mode operations only require clocking in of the opcode and the data byte until the Sequential Program Mode has been exited. AT26F004 6 Address ...
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... MSB HIGH-IMPEDANCE SO Figure 7-2. Read Array - 03h Opcode CS 0 SCK SI 0 MSB HIGH-IMPEDANCE SO 3588D–DFLASH–10/ ADDRESS BITS A23- MSB MSB OPCODE ADDRESS BITS A23- MSB DON'T CARE DATA BYTE MSB MSB DATA BYTE MSB MSB AT26F004 . The 03h SCK . RDLF D 7 ...
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... The Byte Program mode is the default programming mode after the device powers-up or resumes from a device reset. Figure 8-1. Byte Program SCK MSB HIGH-IMPEDANCE SO AT26F004 8 “Protect Sector” on page time to determine if the byte has finished programming. At some point ...
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... Sector 2, the Sequential Byte Program mode would have to be restarted by supplying the AFh opcode, the three address bytes, and the first byte of Sector 2 to program. 3588D–DFLASH–10/08 . For each program cycle, a complete byte of data must be clocked into the device BP AT26F004 9 ...
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... Sequential Byte Program Mode – Waiting Maximum Byte Program Time CS Seqeuntial Program Mode Command SI AFh A A 23-16 15-8 First Address to Program HIGH-IMPEDANCE SO Note: Each transition AT26F004 10 Status Register Read Seqeuntial Program Mode Command Command 05h AFh Data STATUS REGISTER DATA t BP Seqeuntial Program Mode ...
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... WEL bit in the Status Register will be reset back to the logical “0” state. Figure 8-4. 3588D–DFLASH–10/08 time to determine if the device has finished erasing. At BLKE Block Erase SCK OPCODE MSB HIGH-IMPEDANCE SO . BLKE ADDRESS BITS A23- MSB AT26F004 ...
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... For faster throughput recommended that the Status Regis- ter be polled rather than waiting the t some point before the erase cycle completes, the WEL bit in the Status Register will be reset back to the logical “0” state. Figure 8-5. AT26F004 12 . CHPE time to determine if the device has finished erasing. At ...
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... Status Register will be set to a logical “1”. The complete opcode must be clocked into the device before the CS pin is deasserted; otherwise, the device will abort the operation and the state of the WEL bit will not change. Figure 9-1. 3588D–DFLASH–10/08 Write Enable SCK OPCODE MSB HIGH-IMPEDANCE SO AT26F004 ...
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... Status Register will be reset to a logical “0”. The complete opcode must be clocked into the device before the CS pin is deasserted; otherwise, the device will abort the operation and the state of the WEL bit will not change. Figure 9-2. AT26F004 14 “WEL Bit” on page Write Disable ...
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... Sector Protection Register Values Sector Protection Status Sector is unprotected and can be programmed and erased. Sector is protected and cannot be programmed or erased. This is the default state. Protect Sector SCK OPCODE MSB HIGH-IMPEDANCE SO “Status Register Commands” on page ADDRESS BITS A23- MSB AT26F004 ...
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... If the Sector Protection Registers are locked, then any attempts to issue the Unprotect Sector command will be ignored, and the device will reset the WEL bit in the Status Register back to a logical “0” and return to the idle state once the CS pin has been deasserted. Figure 9-4. AT26F004 16 Unprotect Sector CS ...
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... Sector Protection Register Value Sector Protection Register value is 0 (sector is unprotected). Sector Protection Register value is 1 (sector is protected). “Status Register Commands” on page 19 Read Sector Protection Register OPCODE ADDRESS BITS A23- MSB MSB HIGH-IMPEDANCE AT26F004 for more details DATA BYTE MSB D D MSB 17 ...
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... Tables 9-3 and 9-4 Table 9-3. (Don't Care) Note: Table 9-4. WP SPRL AT26F004 18 detail the various protection and locking states of the device. Software Protection Sector Protection Register “n” represents a sector number Hardware and Software Locking Locking SPRL Can be modified from 0 – ...
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... WP is deasserted. 00 All sectors are software unprotected. 01 Some sectors are software protected. Read Sector Protection Registers. R Reserved for future use. 10 All sectors are software protected (default Device is not write enabled (default Device is write enabled. 0 Device is ready Device is busy with an internal operation. AT26F004 19 ...
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... Unprotect Sector operation completes successfully or aborts • Byte Program operation completes successfully or aborts • Sequential Program Mode reaches highest unprotected memory location • Sequential Program Mode reaches the end of the memory array • Sequential Program Mode aborts AT26F004 20 3588D–DFLASH–10/08 ...
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... Status Register data must be continually clocked out of the device until the state of the RDY/BSY bit changes from a logical “1” logical “0”. Figure 10-1. Read Status Register CS SCK SI SO 3588D–DFLASH–10/ OPCODE MSB STATUS REGISTER DATA HIGH-IMPEDANCE MSB AT26F004 STATUS REGISTER DATA MSB MSB 21 ...
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... SPRL bit to a logical “0” while the WP pin is asserted, then the Write Status Register command will be ignored, and the WEL bit in the Status Register will be reset back to the logical “0” state. In order to reset the SPRL bit to a logical “0”, the WP pin must be deasserted. Figure 10-2. Write Status Register AT26F004 ...
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... SO pin into a high-impedance state. The CS pin can be deasserted at any time and does not require that a full byte of data be read. Table 11-1. Byte No. 3588D–DFLASH–10/08 Manufacturer and Device ID Information Data Type 1 Manufacturer ID 2 Device ID (Part 1) 3 Device ID (Part 2) 4 Extended Device Information String Length AT26F004 Value 1FH 04H 00H 00H 23 ...
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... Manufacturer and Device ID Details Data Type Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Manufacturer Family Code Device ID (Part MLC Code Device ID (Part Figure 11-1. Read Manufacturer and Device ID CS SCK SI HIGH-IMPEDANCE SO Note: Each transition AT26F004 24 JEDEC Assigned Code Density Code Product Version Code ...
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... The Deep Power-down command must be reissued after the internally self-timed operation has been completed in order for the device to enter the Deep Power-down mode. Figure 11-2. Deep Power-down 3588D–DFLASH–10/ SCK OPCODE MSB HIGH-IMPEDANCE SO Active Current I CC Standby Mode Current Deep Power-Down Mode Current AT26F004 . EDPD t EDPD ...
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... Read Array can be resumed. If the complete opcode is not clocked in before the CS pin is deasserted, then the device will abort the operation and return to the Deep Power-down mode. Figure 11-3. Resume from Deep Power-down AT26F004 26 and return to the standby mode. After the device RDPD CS ...
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... The WEL bit in the Status Register will be reset back to a logical “0” program, erase, Protect Sector, Unprotect Sector, or Write Status Register operation aborts as a result of the Hold mode aborting. Figure 11-4. Hold Mode CS SCK HOLD 3588D–DFLASH–10/08 Hold Hold AT26F004 Hold 27 ...
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... CMOS levels CS, WP, HOLD = all inputs at CMOS levels MHz mA; OUT Max MHz mA; OUT Max Max Max CMOS levels CMOS levels OUT 0 1.6 mA Min -100 µ 0. AT26F004 -40° 85° C 2.7V to 3.6V Typ Max Units 25 35 µ µ µA 1 µ 3588D–DFLASH–10/08 ...
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... Specification only applies when using the 03h Read Array (Low Frequency) command. 2. Not 100% tested (value guaranteed by design and characterization). 3. Specification only applies when using the SPI Mode 3 timing. 4. Only applicable as a constraint for the Write Status Register command when SPRL = 1. 3588D–DFLASH–10/08 AT26F004 Min Max Units 33 ...
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... Chip Select Low Time CC Power-up Device Delay Before Program or Erase Allowed Power-on Reset Voltage 12.7 Input Test Waveforms and Measurement Levels DRIVING LEVELS < (10 12.8 Output Test Load AT26F004 30 4-Kbyte 32-Kbyte 64-Kbyte 2.4V AC 1.5V 0.45V DEVICE UNDER TEST 30 pF Min Typ ...
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... CSLS SCK MSB HIGH-IMPEDANCE SO Figure 13-2. Serial Output Timing CS SCK Figure 13-3. HOLD Timing – Serial Input CS SCK HOLD SI HIGH-IMPEDANCE SO 3588D–DFLASH–10/08 t CSLH t t SCKH SCKL t DH LSB HHH HLS t HLH t CSH t CSHH t CSHS MSB SCKH SCKL DIS t HHS AT26F004 31 ...
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... SCK t HHH HOLD SI t HLQZ SO Figure 13-5. WP Timing for Write Status Register Command When SPRL = WPS WP SCK SI 0 MSB OF WRITE STATUS REGISTER OPCODE HIGH-IMPEDANCE SO AT26F004 32 t HLS t HLH t HHQX t WPH LSB OF WRITE STATUS REGISTER DATA BYTE t HHS MSB MSB OF NEXT OPCODE ...
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... Green Package Options (Pb/Halide-free/RoHS Compliant) f (MHz) Ordering Code SCK AT26F004-SSU 33 AT26F004-SU AT26F004-MU Note: 1. Contact Atmel for availability. 8S1 8-lead, 0.150” Wide, Plastic Gull Wing Small Outline Package (JEDEC SOIC) 8S2 8-lead, 0.208” Wide, Plastic Gull Wing Small Outline Package (EIAJ SOIC) 8M1-A 8-pad 1.00 mm Very Thin Micro Lead-frame Package (MLF) 3588D– ...
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... Packaging Information 15.1 8S1 – JEDEC SOIC TOP VIEW e e SIDE VIEW Note: These drawings are for general information only. Refer to JEDEC Drawing MS-012, Variation AA for proper dimensions, tolerances, datums, etc. 1150 E. Cheyenne Mtn. Blvd. Colorado Springs, CO 80906 R AT26F004 TITLE 8S1, 8-lead (0.150" Wide Body), Plastic Gull Wing ...
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... TOP VIEW TOP VIEW SIDE VIEW SIDE VIEW TITLE 8S2, 8-lead, 0.208” Body, Plastic Small Outline Package (EIAJ) AT26F004 θ θ END VIEW END VIEW COMMON DIMENSIONS (Unit of Measure = mm) MIN NOM MAX SYMBOL A 1.70 2.16 A1 0.05 ...
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... MLF Pin TOP VIEW Pin #1 Notch e (0. BOTTOM VIEW Package Drawing Contact: packagedrawings@atmel.com AT26F004 0. TITLE 8M1-A, 8-pad 1.00 mm Body, Thermally Enhanced Plastic Very Thin Dual Flat No Lead Package (VDFN) SIDE VIEW A3 A1 0.08 C COMMON DIMENSIONS (Unit of Measure = mm) ...
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... B – January 2006 C – April 2006 D – October 2008 3588D–DFLASH–10/08 History Initial release. Changed t parameter for SPI Mode 3 timing CSLH Changed Note 5 of 8S2 package drawing to generalize terminal plating comment. No longer recommended for new designs. For new designs use AT25DF041A. AT26F004 37 ...
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