CAT24C05YI-GT3 ON Semiconductor, CAT24C05YI-GT3 Datasheet

IC EEPROM 4KBIT 400KHZ 8TSSOP

CAT24C05YI-GT3

Manufacturer Part Number
CAT24C05YI-GT3
Description
IC EEPROM 4KBIT 400KHZ 8TSSOP
Manufacturer
ON Semiconductor
Datasheet

Specifications of CAT24C05YI-GT3

Format - Memory
EEPROMs - Serial
Memory Type
EEPROM
Memory Size
4K (512 x 8)
Speed
400kHz
Interface
I²C, 2-Wire Serial
Voltage - Supply
1.8 V ~ 5.5 V
Operating Temperature
-40°C ~ 85°C
Package / Case
8-TSSOP
Organization
512 x 8
Interface Type
I2C
Maximum Clock Frequency
0.4 MHz
Access Time
900 ns
Supply Voltage (max)
5.5 V
Supply Voltage (min)
1.8 V
Maximum Operating Current
1 mA
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
Operating Supply Voltage
2.5 V, 3.3 V, 5 V
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
24C05YI-GT3
CAT24C05YI-GT3TR

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
CAT24C05YI-GT3
Manufacturer:
ON
Quantity:
120
CAT24C03, CAT24C05
2-Kb and 4-Kb I
EEPROM with Partial Array
Write Protection
Description
organized internally as 16/32 pages of 16 bytes each, for a total of
256x8/512x8 bits. These devices support both Standard (100 kHz) as
well as Fast (400 kHz) I
contiguous bytes into a Page Write Buffer, and then writing all data to
non−volatile memory in one internal write cycle. Data is read by
providing a starting address and then shifting out data serially while
automatically incrementing the internal address count.
taking the WP pin High.
CAT24C03 or four CAT24C05 devices on the same bus.
Features
© Semiconductor Components Industries, LLC, 2009
August, 2009 − Rev. 3
The CAT24C03/05 is a 2−Kb/4−Kb CMOS Serial EEPROM device
Data is written by providing a starting address, then loading 1 to 16
Write operations can be inhibited for upper half of memory by
External address pins make it possible to address up to eight
(SCL and SDA)
Compliant
Supports Standard and Fast I
1.8 V to 5.5 V Supply Voltage Range
16−Byte Page Write Buffer
Hardware Write Protection for Upper Half of Memory
Schmitt Triggers and Noise Suppression Filters on I
Low Power CMOS Technology
1,000,000 Program/Erase Cycles
100 Year Data Retention
Industrial Temperature Range
These Devices are Pb−Free, Halogen Free/BFR Free and are RoHS
A
2
, A
1
SCL
, A
WP
0
Figure 1. Functional Symbol
2
CAT24C03
CAT24C05
C protocol.
V
V
CC
SS
2
C Protocol
2
C Serial
SDA
2
C Bus Inputs
1
See detailed ordering and shipping information in the package
dimensions section on page 14 of this data sheet.
CASE 646AA
L SUFFIX
A0, A1, A2
Pin Name
PDIP−8
CAT24C05/03
SDA
SCL
V
V
WP
NC
NC/A
CC
A
A
SS
SDA
SCL
V
1
2
ORDERING INFORMATION
V
CASE 948AL
/A
/A
SS
SS
PIN CONFIGURATIONS
Y SUFFIX
TSSOP8
0
1
2
TSSOP (Y), TDFN (VP2)
http://onsemi.com
PDIP (L), SOIC (W),
PIN FUNCTION
TSOT−23 (TD)
CASE 419AE
TD SUFFIX
(Top Views)
Device Address Inputs
Serial Data Input/Output
Serial Clock Input
Write Protect Input
Power Supply
Ground
No Connect
TSOT−23
1
2
3
1
2
3
4
Publication Order Number:
CASE 511AK
5
4
VP2 SUFFIX
8
7
6
5
Function
TDFN8
CASE 751BD
WP
V
V
WP
SCL
SDA
CC
CAT24C03/D
W SUFFIX
CC
SOIC−8

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CAT24C05YI-GT3 Summary of contents

Page 1

... Data is written by providing a starting address, then loading contiguous bytes into a Page Write Buffer, and then writing all data to non−volatile memory in one internal write cycle. Data is read by providing a starting address and then shifting out data serially while automatically incrementing the internal address count. ...

Page 2

Table 1. ABSOLUTE MAXIMUM RATINGS Parameters Storage Temperature Voltage on any pin with respect to Ground (Note 1) Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is ...

Page 3

Table 4. PIN IMPEDANCE CHARACTERISTICS ( −40°C to +85°C, unless otherwise specified Symbol Parameter C (Note 4) SDA I/O Pin Capacitance IN Input Capacitance (Other Pins) I (Note 5) WP ...

Page 4

... When not driven, these pins are pulled LOW internally. WP: The Write Protect input pin inhibits the write operations for upper half of memory, when pulled HIGH. When not driven, this pin is pulled LOW internally. Functional Description The CAT24C03/05 supports the Inter−Integrated Circuit ...

Page 5

SCL SDA START CONDITION BUS RELEASE DELAY (TRANSMITTER) SCL FROM MASTER DATA OUTPUT FROM TRANSMITTER DATA OUTPUT FROM RECEIVER START SCL t SU:STA t HD:STA SDA IN SDA OUT Figure 2. START/STOP Conditions ...

Page 6

... ACK will be returned and the host can then proceed with the next read or write operation. Hardware Write Protection With the WP pin held HIGH, the upper half of memory is protected against Write operations. If the WP pin is left floating or is grounded, it has no impact on the operation of the CAT24C03/05 ...

Page 7

SCL th SDA 8 Bit Byte n S BUS ACTIVITY SLAVE R MASTER ADDRESS SLAVE ADDRESS BYTE 1 SCL a 7 SDA WP ACK t WR STOP ...

Page 8

... CAT24C03/05 will continue transmitting data residing at subsequent locations until the Master responds with a NoACK, followed by a STOP (Figure 12). In contrast to Page Write, during Sequential Read the address count will automatically increment to and then wrap−around at end of memory (rather than end of page SLAVE ...

Page 9

PIN # 1 IDENTIFICATION D TOP VIEW SIDE VIEW Notes: (1) All dimensions are in millimeters. (2) Complies with JEDEC MS-001. PACKAGE DIMENSIONS PDIP−8, 300 mils CASE 646AA−01 ISSUE A SYMBOL ...

Page 10

PIN # 1 IDENTIFICATION TOP VIEW SIDE VIEW Notes: (1) All dimensions are in millimeters. Angles in degrees. (2) Complies with JEDEC MS-012. PACKAGE DIMENSIONS SOIC 8, 150 mils CASE 751BD−01 ISSUE O SYMBOL ...

Page 11

E1 e TOP VIEW SIDE VIEW Notes: (1) All dimensions are in millimeters. Angles in degrees. (2) Complies with JEDEC MO-153. PACKAGE DIMENSIONS TSSOP8, 4.4x3 CASE 948AL−01 ISSUE O SYMBOL MIN A A1 0.05 A2 ...

Page 12

D E PIN#1 INDEX AREA TOP VIEW SYMBOL MIN NOM A 0.70 0.75 A1 0.00 0.02 A2 0.45 0.55 A3 0.20 REF b 0.20 0.25 D 1.90 2.00 D2 1.30 1.40 E 2.90 3.00 E2 1.20 1.30 e 0.50 TYP ...

Page 13

TOP VIEW SIDE VIEW Notes: (1) All dimensions are in millimeters. Angles in degrees. (2) Complies with JEDEC MO-193. PACKAGE DIMENSIONS TSOT−23, 5 LEAD CASE 419AE−01 ISSUE O SYMBOL MIN A A1 0.01 A2 ...

Page 14

... The device used in the above example is a CAT24C03YI−GT3 (TSSOP, Industrial Temperature, NiPdAu, Tape & Reel). 12. For additional package and temperature options, please contact your nearest ON Semiconductor Sales office. 13. For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D ...

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