CY7C1470V33-167BZXC Cypress Semiconductor Corp, CY7C1470V33-167BZXC Datasheet

Page 1

... FBGA package ■ IEEE 1149.1 JTAG Boundary Scan compatible ■ Burst Capability—Linear or Interleaved Burst Order ■ “ZZ” Sleep Mode option and Stop Clock option Logic Block Diagram – CY7C1470V33 (2M x 36) A0, A1, A MODE CLK C CEN WRITE ADDRESS ...

Page 2

... REGISTER 1 READ LOGIC Sleep Control ADDRESS REGISTER BURST A0 LOGIC ADV/LD C WRITE ADDRESS REGISTER 2 WRITE REGISTRY MEMORY AND DATA COHERENCY WRITE ARRAY CONTROL LOGIC DRIVERS INPUT E REGISTER 1 READ LOGIC Sleep Control 250 MHz 200 MHz 3.0 500 120 CY7C1470V33 CY7C1472V33 CY7C1474V33 ...

Page 3

... DQa 18 63 DQa DQb DDQ 20 61 DDQ DQa DQb 22 59 DQa DQb 23 58 DQa DQPb 24 57 DQa DDQ 27 54 DDQ DQa DQa DQPa CY7C1470V33 CY7C1472V33 CY7C1474V33 DDQ DQPa 74 DQa 73 DQa DDQ DQa 69 DQa CY7C1472V33 ( DQa 63 DQa DDQ DQa 59 DQa 58 NC ...

Page 4

... DDQ DDQ DDQ DDQ DDQ N DQP DDQ P NC/144M MODE NC/576M NC/1G A CE2 DDQ DDQ DDQ DDQ DDQ DDQ DDQ DDQ DDQ N DQP DDQ P NC/144M MODE A Document #: 38-05289 Rev. *J CY7C1470V33 ( CEN CLK TDI A1 TDO TCK TMS CY7C1472V33 ( CEN CLK ...

Page 5

... CEN DDQ DDQ DDQ MODE TDI CY7C1470V33 CY7C1472V33 CY7C1474V33 DQb DQb 3 BWS BWS DQb DQb b f BWS BWS DQb DQb DQb DQb DQPf DQPb DDQ DDQ V DQf V DQf DQf DQf DDQ DDQ V V DQf SS SS DQf V V DDQ DQf DQf DDQ NC ...

Page 6

... The direction of the pins is [17:0] –DQ are placed in a tristate condition. The outputs are automati controlled DQP controlled DQP is controlled DQP is controlled CY7C1470V33 CY7C1472V33 CY7C1474V33 and DQP , BW controls DQ and DQP controls DQ and DQP , ...

Page 7

... During normal operation, this pin has to be LOW or left floating. ZZ pin has an internal pull down. Functional Overview The CY7C1470V33, CY7C1472V33, and CY7C1474V33 are synchronous-pipelined Burst NoBL SRAMs designed specifi- cally to eliminate wait states during Write/Read transitions. All synchronous inputs pass through input registers controlled by the rising edge of the clock ...

Page 8

... CY7C1472V33) are automatically tristated during the data portion of a Write cycle, regardless of the state of OE. Burst Write Accesses The CY7C1470V33, CY7C1472V33, and CY7C1474V33 has an on-chip burst counter that allows the user the ability to supply a single address and conduct up to four Write operations without reasserting the address inputs ...

Page 9

... Truth Table The Truth Table for parts CY7C1470V33/CY7C1472V33/CY7C1474V33 is as follows. Operation Address Used Deselect Cycle None Continue None Deselect Cycle Read Cycle External (Begin Burst) Read Cycle Next (Continue Burst) NOP/Dummy Read External (Begin Burst) Dummy Read Next (Continue Burst) Write Cycle ...

Page 10

... Partial Write Cycle Description The Partial Write Cycle Description for parts CY7C1470V33/CY7C1472V33/CY7C1474V33 is as follows. Function (CY7C1470V33) Read Write – No bytes written Write Byte a – (DQ and DQP ) a a Write Byte b – (DQ and DQP ) b b Write Bytes b, a Write Byte c – (DQ and DQP ...

Page 11

... IEEE 1149.1 Serial Boundary Scan (JTAG) The CY7C1470V33, CY7C1472V33, and CY7C1474V33 incor- porates a serial boundary scan test access port (TAP). This port operates in accordance with IEEE Standard 1149.1-1990 but does not have the set of functions required for full 1149.1 compliance. These functions from the IEEE specification are excluded because their inclusion places an added delay in the critical speed path of the SRAM ...

Page 12

... Repeatable results may not be possible. To guarantee that the boundary scan register will capture the correct value of a signal, the SRAM signal must be stabilized long enough to meet the TAP controller’s capture setup plus hold time (t plus CY7C1470V33 CY7C1472V33 CY7C1474V33 Page [+] Feedback ...

Page 13

... Reserved These instructions are not implemented but are reserved for future use. Do not use these instructions TDIS t TDIH t TDOX DON’ UNDEFINED [9, 10] Over the Operating Range Description / ns CY7C1470V33 CY7C1472V33 CY7C1474V33 TDOV Min Max Unit MHz ...

Page 14

... 2.5V OL DDQ I = 100 µ 3.3V OL DDQ V = 2.5V DDQ V = 3.3V DDQ V = 2.5V DDQ V = 3.3V DDQ V = 2.5V DDQ GND < V < DDQ CY7C1470V33 CY7C1472V33 CY7C1474V33 to 2.5V SS 1.25V 50Ω 50Ω 20pF O Min Max Unit 2.4 V 2.0 V 2.9 V 2.1 V 0.4 V 0.4 V 0.2 V 0 0.3 ...

Page 15

... Captures I/O ring contents. Places the boundary scan register between TDI and TDO. Does not affect SRAM operation. This instruction does not implement 1149.1 preload function and is therefore not 1149.1 compliant. Do Not Use: This instruction is reserved for future use. CY7C1470V33 CY7C1472V33 CY7C1474V33 Description ...

Page 16

... L10 59 B8 K11 60 A7 165-Ball ID Bit # 165-Ball L10 P6 28 K10 R6 29 J10 R8 30 H11 P3 31 G11 P4 32 F11 P8 33 E11 P9 34 D11 P10 35 C11 R9 36 A11 R10 37 A9 R11 38 B9 M10 39 A10 CY7C1470V33 CY7C1472V33 CY7C1474V33 Bit # 165-Ball Bit # 165-Ball ID 40 B10 ...

Page 17

... J11 V5 72 J10 U5 73 H11 U6 74 H10 W7 75 G11 V7 76 G10 U7 77 F11 V8 78 F10 V9 79 E10 W11 80 E11 W10 81 D11 V11 82 D10 V10 83 C11 U11 84 C10 CY7C1470V33 CY7C1472V33 CY7C1474V33 Bit # 209-Ball ID 85 B11 86 B10 87 A11 88 A10 100 B3 101 C3 102 C4 103 ...

Page 18

... Input = V DD ≤ V Output Disabled I DDQ, /2), undershoot: V (AC)> –2V (Pulse width less than t CYC IL (Min) within 200 ms. During this time V < CY7C1470V33 CY7C1472V33 CY7C1474V33 Test Conditions Typ Max* Unit Logical 25°C 361 394 Single Bit Upsets Logical Multi 25°C 0 0.01 Bit Upsets Single Event 85° ...

Page 19

... IN IL Test Conditions T = 25° MHz 3. 2.5V DDQ 100 TQFP Test Conditions Package Test conditions follow standard 24.63 test methods and procedures for measuring thermal impedance, per EIA/JESD51. CY7C1470V33 CY7C1472V33 CY7C1474V33 Min Max Unit 500 mA 500 mA 450 mA 245 mA 245 mA 245 mA 120 mA ...

Page 20

... V OUTPUT GND 351Ω INCLUDING JIG AND (b) SCOPE R = 1667Ω 2.5V V DDQ OUTPUT GND 1538Ω INCLUDING JIG AND (b) SCOPE CY7C1470V33 CY7C1472V33 CY7C1474V33 ALL INPUT PULSES DDQ 90% 90% 10% 10% ≤ ≤ (c) ALL INPUT PULSES 90% 90% 10% 10% ≤ ≤ (c) Page [+] Feedback ...

Page 21

... V minimum initially, before a Read or Write operation can DD and t is less than t to eliminate bus contention between SRAMs when sharing the same data EOLZ CHZ CLZ CY7C1470V33 CY7C1472V33 CY7C1474V33 –200 –167 Unit Min Max Min ...

Page 22

... DOH CLZ D(A1) D(A2) Q(A3) D(A2+1) t OEHZ BURST READ READ BURST WRITE Q(A3) Q(A4) READ Q(A4+1) DON’T CARE UNDEFINED is LOW. When CE is HIGH HIGH CY7C1470V33 CY7C1472V33 CY7C1474V33 OEV CHZ Q(A4) Q(A4+1) D(A5) Q(A6) t DOH t OELZ WRITE READ WRITE DESELECT ...

Page 23

... A3 A4 D(A1) Q(A2) Q(A3) READ WRITE STALL NOP Q(A3) D(A4) DON’T CARE UNDEFINED [26, 27] Figure 9. ZZ Mode Timing High-Z DON’T CARE CY7C1470V33 CY7C1472V33 CY7C1474V33 CHZ D(A4) Q(A5) READ DESELECT CONTINUE Q(A5) DESELECT t ZZREC t RZZI DESELECT or READ Only Page [+] Feedback ...

Page 24

... CY7C1470V33-167AXC 51-85050 100-Pin Thin Quad Flat Pack ( 1.4 mm) Pb-Free CY7C1470V33-167BZC 51-85165 165-ball Fine-Pitch Ball Grid Array ( 1.4mm) CY7C1470V33-167BZXC 51-85165 165-ball Fine-Pitch Ball Grid Array ( 1.4mm) Pb-Free CY7C1474V33-167BGC 51-85167 209-ball Fine-Pitch Ball Grid Array (14 × 22 × 1.76 mm) CY7C1470V33-167AXI 51-85050 100-Pin Thin Quad Flat Pack ( 1.4 mm) Pb-Free ...

Page 25

... BODY LENGTH DIMENSION DOES NOT INCLUDE MOLD PROTRUSION/END FLASH MOLD PROTRUSION/END FLASH SHALL NOT EXCEED 0.0098 in (0.25 mm) PER SIDE BODY LENGTH DIMENSIONS ARE MAX PLASTIC BODY SIZE INCLUDING MOLD MISMATCH 0.20 MAX. 3. DIMENSIONS IN MILLIMETERS A CY7C1470V33 CY7C1472V33 CY7C1474V33 1.40±0.05 12°±1° SEE DETAIL (8X) 0 ...

Page 26

... Package Diagrams (continued) Document #: 38-05289 Rev. *J Figure 11. 165-ball FBGA ( 1.4 mm) CY7C1470V33 CY7C1472V33 CY7C1474V33 51-85165 *B Page [+] Feedback ...

Page 27

... Package Diagrams (continued) Document #: 38-05289 Rev. *J Figure 12. 209-ball FBGA ( 1.76 mm) CY7C1470V33 CY7C1472V33 CY7C1474V33 51-85167 ** Page [+] Feedback ...

Page 28

... Document History Page Document Title: CY7C1470V33/CY7C1472V33/CY7C1474V33, 72 Mbit (2M x 36/4M x 18/1M x 72) Pipelined SRAM with NoBL™ Architecture Document Number: 38-05289 Orig. of Submission Revision ECN Change ** 114676 PKS *A 121520 CJM *B 223721 NJY *C 235012 RYQ *D 243572 NJY *E 299511 SYT VBL *F 323039 PCI *G 351937 PCI Document #: 38-05289 Rev ...

Page 29

... Document Title: CY7C1470V33/CY7C1472V33/CY7C1474V33, 72 Mbit (2M x 36/4M x 18/1M x 72) Pipelined SRAM with NoBL™ Architecture Document Number: 38-05289 Orig. of Submission Revision ECN Change *H 416221 RXU *I 472335 VKN *J 2756998 VKN Document #: 38-05289 Rev. *J Description of Change Date See ECN Converted from Preliminary to Final Changed address of Cypress Semiconductor Corporation on Page# 1 from “ ...

Page 30

... Use may be limited by and subject to the applicable Cypress software license agreement. Document #: 38-05289 Rev NoBL and No Bus Latency are trademarks of Cypress Semiconductor Corporation. All products and company names mentioned in this document may be the trademarks of their respective holders. psoc.cypress.com clocks.cypress.com image.cypress.com Revised August 16, 2009 CY7C1470V33 CY7C1472V33 CY7C1474V33 Page [+] Feedback ...