CY7C1515AV18-200BZXI Cypress Semiconductor Corp, CY7C1515AV18-200BZXI Datasheet

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... Because data can be trans- ferred into and out of the device on every rising edge of both input clocks (K and K and C and C), memory bandwidth is maximized ...

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... D [8:0] 21 Address A (20:0) Register K CLK K Gen. DOFF V REF Control WPS Logic BWS [0] Document Number: 001-06985 Rev. *D CY7C1511AV18, CY7C1526AV18 CY7C1513AV18, CY7C1515AV18 Write Write Write Write Address Reg Reg Reg Reg Register Control Logic Read Data Reg Reg. Reg. 16 Reg. Write Write ...

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... Logic Block Diagram (CY7C1513AV18 [17:0] 20 Address A (19:0) Register K CLK K Gen. DOFF V REF Control WPS Logic BWS [1:0] Logic Block Diagram (CY7C1515AV18 [35:0] 19 Address A (18:0) Register K CLK K Gen. DOFF V REF Control WPS Logic BWS [3:0] Document Number: 001-06985 Rev. *D CY7C1511AV18, CY7C1526AV18 CY7C1513AV18, CY7C1515AV18 ...

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... Pin Configuration The pin configuration for CY7C1511AV18, CY7C1526AV18, CY7C1513AV18, and CY7C1515AV18 follow DOFF V V REF DDQ TDO TCK DOFF V V REF DDQ TDO TCK A Note 1. NC/144M and NC/288M are not connected to the die and can be tied to any voltage level. Document Number: 001-06985 Rev. *D ...

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... Pin Configuration (continued) The pin configuration for CY7C1511AV18, CY7C1526AV18, CY7C1513AV18, and CY7C1515AV18 follow NC/144M D10 D NC D11 Q10 Q11 F NC Q12 D12 G NC D13 Q13 H DOFF V V REF DDQ D14 Q14 L NC Q15 D15 D16 N NC D17 Q16 Q17 R TDO TCK ...

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... CY7C1511AV18 arrays each for CY7C1526AV18 arrays each 18) for CY7C1513AV18 and arrays each of 512K x 36) for CY7C1515AV18. Therefore, only 21 address inputs are needed to access the entire memory array of CY7C1511AV18 and CY7C1526AV18, 20 address inputs for CY7C1513AV18 and 19 address inputs for CY7C1515AV18 ...

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... Ground for the Device Power Supply Power Supply Inputs for the Outputs of the Device. DDQ Document Number: 001-06985 Rev. *D CY7C1511AV18, CY7C1526AV18 CY7C1513AV18, CY7C1515AV18 Pin Description Switching Characteristics on page 24. output impedance are set to 0.2 x RQ, where resistor connected [x:0] , which enables the ...

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... Functional Overview The CY7C1511AV18, CY7C1526AV18, CY7C1515AV18 are synchronous pipelined Burst SRAMs with a read port and a write port. The read port is dedicated to read operations and the write port is dedicated to write operations. Data flows into the SRAM through the write port and flows out through the read port ...

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... All pending transactions (read and write) are completed before the device is deselected. Document Number: 001-06985 Rev. *D CY7C1511AV18, CY7C1526AV18 CY7C1513AV18, CY7C1515AV18 Programmable Impedance An external resistor, RQ, must be connected between the ZQ pin on the SRAM and V to allow the SRAM to adjust its output SS driver impedance ...

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... BWS# (CPU CLKIN/CLKIN# or Source K ASIC) Source K# Delayed K Delayed 50ohms Truth Table The truth table for CY7C1511AV18, CY7C1526AV18, CY7C1513AV18, and CY7C1515AV18 follows. Operation K RPS WPS [8] Write Cycle: L-H H Load address on the rising edge of K; input write data on two consecutive K and K rising edges. ...

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... Note 10. Is based on a write cycle that was initiated in accordance with the different portions of a write cycle, as long as the setup and hold requirements are achieved. Document Number: 001-06985 Rev. *D CY7C1511AV18, CY7C1526AV18 CY7C1513AV18, CY7C1515AV18 [2, 10] Comments ) are written into the device, [7:0] ) are written into the device ...

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... Write Cycle Descriptions The write cycle description table for CY7C1515AV18 follows. BWS BWS BWS BWS L– – L– – L– – L– – L– – L– – Document Number: 001-06985 Rev. *D CY7C1511AV18, CY7C1526AV18 CY7C1513AV18, CY7C1515AV18 [2, 10] K Comments – During the Data portion of a write sequence, all four bytes (D the device. L– ...

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... TDI pin on the rising edge of TCK. Data is output on the TDO pin on the falling edge of TCK. Document Number: 001-06985 Rev. *D CY7C1511AV18, CY7C1526AV18 CY7C1513AV18, CY7C1515AV18 Instruction Register Three-bit instructions can be serially loaded into the instruction register. This register is loaded when it is placed between the TDI and TDO pins, as shown in page 16 ...

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... TAP into the Shift-DR state. This places the boundary scan register between the TDI and TDO pins. Document Number: 001-06985 Rev. *D CY7C1511AV18, CY7C1526AV18 CY7C1513AV18, CY7C1515AV18 PRELOAD places an initial data pattern at the latched parallel outputs of the boundary scan register cells before the selection of another boundary scan test operation. ...

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... The state diagram for the TAP controller follows. TEST-LOGIC 1 RESET 0 1 TEST-LOGIC/ 0 IDLE Note 11. The 0/1 next to each state represents the value at TMS at the rising edge of TCK. Document Number: 001-06985 Rev. *D CY7C1511AV18, CY7C1526AV18 CY7C1513AV18, CY7C1515AV18 [11] 1 SELECT DR-SCAN 0 1 CAPTURE- SHIFT- ...

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... These characteristics pertain to the TAP inputs (TMS, TCK, TDI and TDO). Parallel load levels are specified in the 13. Overshoot: V (AC) < 0.85V (Pulse width less than t IH DDQ 14. All Voltage referenced to Ground. Document Number: 001-06985 Rev. *D CY7C1511AV18, CY7C1526AV18 CY7C1513AV18, CY7C1515AV18 0 Bypass Register Instruction Register ...

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... CS CH 16. Test conditions are specified using the load in TAP AC Test Conditions. t Document Number: 001-06985 Rev. *D CY7C1511AV18, CY7C1526AV18 CY7C1513AV18, CY7C1515AV18 Description [16] Figure 2. TAP Timing and Test Conditions 0.9V 1.8V 50Ω ...

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... Do Not Use: This instruction is reserved for future use. BYPASS 111 Places the bypass register between TDI and TDO. This operation does not affect SRAM operation. Document Number: 001-06985 Rev. *D CY7C1511AV18, CY7C1526AV18 CY7C1513AV18, CY7C1515AV18 Value CY7C1526AV18 CY7C1513AV18 000 000 00000110100 00000110100 ...

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... Document Number: 001-06985 Rev. *D CY7C1511AV18, CY7C1526AV18 CY7C1513AV18, CY7C1515AV18 Bump ID Bit # Bump ID 10G 11F 58 5A 11G 10F 61 4B 11E 62 3A 10E 63 2A 10D 10C 66 3B 11D ...

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... DDQ DOFF Document Number: 001-06985 Rev. *D CY7C1511AV18, CY7C1526AV18 CY7C1513AV18, CY7C1515AV18 DLL Constraints ■ DLL uses K clock as its synchronizing input. The input must have low phase jitter, which is specified as t ■ The DLL functions at frequencies down to 120 MHz. ■ If the input clock is unstable and the DLL is enabled, then the DLL may lock onto an incorrect frequency, causing unstable SRAM behavior ...

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... V REF DDQ 21. The operation current is calculated with 50% read cycle and 50% write cycle. Document Number: 001-06985 Rev. *D CY7C1511AV18, CY7C1526AV18 CY7C1513AV18, CY7C1515AV18 Current into Outputs (LOW) ........................................ 20 mA Static Discharge Voltage (MIL-STD-883, M. 3015).. > 2001V Latch-up Current ................................................... > 200 mA Operating Range Range Commercial ...

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... DD I Automatic Power down SB1 Current AC Electrical Characteristics [13] Over the Operating Range Parameter Description V Input HIGH Voltage IH V Input LOW Voltage IL Document Number: 001-06985 Rev. *D CY7C1511AV18, CY7C1526AV18 CY7C1513AV18, CY7C1515AV18 Test Conditions V = Max, 200MHz (x8 mA, OUT (x9 1/t MAX CYC (x18) (x36) 167MHz ...

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... Unless otherwise noted, test conditions are based on signal transition time of 2V/ns, timing reference levels of 0.75V, Vref = 0.75V 250Ω, V pulse levels of 0.25V to 1.25V, and output loading of the specified I Document Number: 001-06985 Rev. *D CY7C1511AV18, CY7C1526AV18 CY7C1513AV18, CY7C1515AV18 Test Conditions T = 25° MHz ...

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... This part has a voltage regulator internally; t POWER initiated. 25. For D0 data signal on CY7C1526AV18 device, t Document Number: 001-06985 Rev. *D CY7C1511AV18, CY7C1526AV18 CY7C1513AV18, CY7C1515AV18 300 MHz 278 MHz Min Max Min Max Min Max Min Max Min Max [24 ...

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... CHZ CLZ 28. At any voltage and temperature t is less than t CHZ Document Number: 001-06985 Rev. *D CY7C1511AV18, CY7C1526AV18 CY7C1513AV18, CY7C1515AV18 300 MHz 278 MHz Min Max Min Max Min Max Min Max Min Max – 0.45 – 0.45 – ...

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... Outputs are disabled (High-Z) one clock cycle after a NOP. 31. In this example, if address A2 = A1, then data Q20 = D10, Q21 = D11, Q22 = D12, and Q23 = D13. Write data is forwarded immediately as read results. This note applies to the whole diagram. Document Number: 001-06985 Rev. *D CY7C1511AV18, CY7C1526AV18 CY7C1513AV18, CY7C1515AV18 [29, 30, 31] WRITE READ WRITE ...

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... CY7C1511AV18-278BZXI CY7C1526AV18-278BZXI CY7C1513AV18-278BZXI CY7C1515AV18-278BZXI Document Number: 001-06985 Rev. *D CY7C1511AV18, CY7C1526AV18 CY7C1513AV18, CY7C1515AV18 Package Diagram Package Type 51-85195 165-Ball Fine Pitch Ball Grid Array ( 1.4 mm) 51-85195 165-Ball Fine Pitch Ball Grid Array ( 1.4 mm) Pb-Free 51-85195 165-Ball Fine Pitch Ball Grid Array ( 1.4 mm) 51-85195 165-Ball Fine Pitch Ball Grid Array ( ...

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... CY7C1513AV18-200BZXC CY7C1515AV18-200BZXC CY7C1511AV18-200BZI CY7C1526AV18-200BZI CY7C1513AV18-200BZI CY7C1515AV18-200BZI CY7C1511AV18-200BZXI CY7C1526AV18-200BZXI CY7C1513AV18-200BZXI CY7C1515AV18-200BZXI Document Number: 001-06985 Rev. *D CY7C1511AV18, CY7C1526AV18 CY7C1513AV18, CY7C1515AV18 Package Diagram Package Type 51-85195 165-Ball Fine Pitch Ball Grid Array ( 1.4 mm) 51-85195 165-Ball Fine Pitch Ball Grid Array ( 1.4 mm) Pb-Free 51-85195 165-Ball Fine Pitch Ball Grid Array ( 1.4 mm) 51-85195 165-Ball Fine Pitch Ball Grid Array ( ...

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... CY7C1511AV18-167BZXI CY7C1526AV18-167BZXI CY7C1513AV18-167BZXI CY7C1515AV18-167BZXI Document Number: 001-06985 Rev. *D CY7C1511AV18, CY7C1526AV18 CY7C1513AV18, CY7C1515AV18 Package Diagram Package Type 51-85195 165-Ball Fine Pitch Ball Grid Array ( 1.4 mm) 51-85195 165-Ball Fine Pitch Ball Grid Array ( 1.4 mm) Pb-Free 51-85195 165-Ball Fine Pitch Ball Grid Array ( 1.4 mm) 51-85195 165-Ball Fine Pitch Ball Grid Array ( ...

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... Package Diagram Figure 6. 165-ball FBGA ( 1.4 mm), 51-85195 Document Number: 001-06985 Rev. *D CY7C1511AV18, CY7C1526AV18 CY7C1513AV18, CY7C1515AV18 51-85195-*A Page [+] Feedback [+] Feedback ...

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... Document History Page Document Title: CY7C1511AV18/CY7C1526AV18/CY7C1513AV18/CY7C1515AV18, 72-Mbit QDR™-II SRAM 4-Word Burst Architecture Document Number: 001-06985 SUBMISSION ORIG. OF REV. ECN NO. DATE CHANGE ** 433241 See ECN *A 462002 See ECN *B 850381 See ECN *C 1523363 See ECN VKN/AESA Converted from preliminary to final, Updated Logic Block diagram ...