CY7C1383D-133AXC Cypress Semiconductor Corp, CY7C1383D-133AXC Datasheet - Page 20

• Manufacturer Part Number: CY7C1383D-133AXC
• Description: IC SRAM 18MBIT 133MHZ 100LQFP
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY7C1383D-133AXC

• Memory Size: 18M (1M x 18)
• Format - Memory: RAM
• Memory Type: SRAM - Synchronous
• Speed: 133MHz
• Interface: Parallel
• Voltage - Supply: 3.135 V ~ 3.6 V
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 100-LQFP
• Memory Configuration: 1M X 18 / 512K X 36
• Clock Frequency: 133MHz
• Access Time: 6.5ns
• Supply Voltage Range: 3.135V To 3.6V
• Memory Case Style: TQFP
• No. Of Pins: 100
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 428-1848

Switching Characteristics
Over the Operating Range
Document #: 38-05544 Rev. *F
Notes:
20. Timing reference level is 1.5V when V
21. Test conditions shown in (a) of AC Test Loads unless otherwise noted.
22. This part has a voltage regulator internally; t
23. t
24. At any given voltage and temperature, t
25. This parameter is sampled and not 100% tested.
t
Clock
t
t
t
Output Times
t
t
t
t
t
t
t
Setup Times
t
t
t
t
t
t
Hold Times
t
t
t
t
t
t
POWER
CYC
CH
CL
CDV
DOH
CLZ
CHZ
OEV
OELZ
OEHZ
AS
ADS
ADVS
WES
DS
CES
AH
ADH
WEH
ADVH
DH
CEH
can be initiated.
mV from steady-state voltage.
data bus. These specifications do not imply a bus contention condition, but reflect parameters guaranteed over worst case user conditions. Device is designed to
achieve High-Z prior to Low-Z under the same system condition.
CHZ
, t
Parameter
CLZ
,t
OELZ
, and t
OEHZ
are specified with AC test conditions shown in part (b) of
V
Clock Cycle Time
Clock HIGH
Clock LOW
Data Output Valid After CLK Rise
Data Output Hold After CLK Rise
Clock to Low-Z
Clock to High-Z
OE LOW to Output Valid
OE LOW to Output Low-Z
OE HIGH to Output High-Z
Address Setup Before CLK Rise
ADSP, ADSC Setup Before CLK Rise
ADV Setup Before CLK Rise
GW, BWE, BW
Data Input Setup Before CLK Rise
Chip Enable Setup
Address Hold After CLK Rise
ADSP, ADSC Hold After CLK Rise
GW, BWE, BW
ADV Hold After CLK Rise
Data Input Hold After CLK Rise
Chip Enable Hold After CLK Rise
DD
[20, 21]
(Typical) to the first Access
DDQ
OEHZ
= 3.3V and is 1.25V when V
POWER
is less than t
[A:D]
[A:D]
Description
[23, 24, 25]
[23, 24, 25]
is the time that the power needs to be supplied above V
Setup Before CLK Rise
Hold After CLK Rise
OELZ
[23, 24, 25]
and t
[23, 24, 25]
CHZ
[22]
DDQ
is less than t
= 2.5V.
AC Test Loads and Waveforms on page
CLZ
to eliminate bus contention between SRAMs when sharing the same
Min
1.5
1.5
1.5
7.5
2.1
2.1
2.0
2.0
1.5
1.5
1.5
0.5
0.5
0.5
0.5
0.5
0.5
1
0
0
133 MHz
CY7C1381D, CY7C1381F
CY7C1383D, CY7C1383F
Max
DD
4.0
3.2
4.0
6.5
(minimum) initially, before a read or write operation
Min
2.5
2.5
2.0
2.0
1.5
1.5
1.5
1.5
1.5
1.5
0.5
0.5
0.5
0.5
0.5
0.5
10
1
0
0
19. Transition is measured ± 200
100 MHz
Max
8.5
5.0
3.8
5.0
Page 20 of 29
Unit
ms
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
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