CY62167EV30LL-45BVXI Cypress Semiconductor Corp, CY62167EV30LL-45BVXI Datasheet - Page 7

• Manufacturer Part Number: CY62167EV30LL-45BVXI
• Description: IC SRAM 16MBIT 45NS 48VFBGA
• Manufacturer: Cypress Semiconductor Corp
• Type: Asynchronousr

Specifications of CY62167EV30LL-45BVXI

• Memory Size: 16M (2M x 8 or 1M x 16)
• Package / Case: 48-VFBGA
• Format - Memory: RAM
• Memory Type: SRAM
• Speed: 45ns
• Interface: Parallel
• Voltage - Supply: 2.2 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Access Time: 45 ns
• Supply Voltage (max): 3.6 V
• Supply Voltage (min): 2.2 V
• Maximum Operating Current: 30 mA
• Organization: 1 M x 16
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Number Of Ports: 1
• Operating Supply Voltage: 2.5 V or 3.3 V
• Memory Configuration: 2M X 8 / 1M X 16
• Supply Voltage Range: 2.2V To 3.6V
• Memory Case Style: BGA
• No. Of Pins: 48
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

Switching Characteristics
Notes
Document #: 38-05446 Rev. *I
READ CYCLE
t
t
t
t
t
t
t
t
t
t
t
t
t
t
WRITE CYCLE
t
t
t
t
t
t
t
t
t
t
t
18. Test conditions for all parameters other than tristate parameters assume signal transition time of 1 V/ns, timing reference levels of V
19. AC timing parameters are subject to byte enable signals (BHE or BLE) not switching when chip is disabled. See
20. At any temperature and voltage condition, t
21. t
22. The internal write time of the memory is defined by the overlap of WE, CE
RC
AA
OHA
ACE
DOE
LZOE
HZOE
LZCE
HZCE
PU
PD
DBE
LZBE
HZBE
WC
SCE
AW
HA
SA
PWE
BW
SD
HD
HZWE
LZWE
Parameter
to V
write and any of these signals can terminate a write by going INACTIVE. The data input setup and hold timing must refer to the edge of the signal that terminates the write.
HZOE
CC
, t
(typ), and output loading of the specified I
HZCE
, t
[18, 19]
HZBE
[22]
, and t
Read cycle time
Address to data valid
Data hold from address change
CE
OE LOW to data valid
OE LOW to LOW Z
OE HIGH to High Z
CE
CE
CE
CE
BLE / BHE LOW to data valid
BLE / BHE LOW to Low Z
BLE / BHE HIGH to HIGH Z
Write cycle time
CE
Address setup to write end
Address hold from write end
Address setup to write start
WE pulse width
BLE / BHE LOW to write end
Data setup to write end
Data hold from write end
WE LOW to High Z
WE HIGH to Low Z
HZWE
1
1
1
1
1
1
LOW and CE
LOW and CE
HIGH and CE
LOW and CE
HIGH and CE
LOW and CE
transitions are measured when the outputs enter a high impedance state.
HZCE
2
2
2
2
2
2
[20, 21]
[20]
[20]
[20, 21]
HIGH to data valid
HIGH to Low Z
HIGH to power-up
HIGH to write end
OL
LOW to High Z
LOW to power-down
is less than t
/I
OH
as shown in
[20]
[20, 21]
Description
LZCE
, t
[20]
[20, 21]
“AC Test Loads and Waveforms”
HZBE
is less than t
1
= V
IL
, BHE or BLE or both = V
LZBE
, t
HZOE
is less than t
on page 5.
IL
, and CE
LZOE
application note AN13842
, and t
2
45 ns (Industrial/Auto-A)
= V
CY62167EV30 MoBL
IH
HZWE
Min
. All signals must be ACTIVE to initiate a
45
10
10
10
45
35
35
35
35
25
10
–
–
–
5
–
–
0
–
–
–
0
0
0
–
is less than t
CC
(typ)/2, input pulse levels of 0
for further clarification.
Max
LZWE
45
45
22
18
18
45
45
18
18
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
for any device.
Page 7 of 16
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
®
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