M48Z02-150PC1 STMicroelectronics, M48Z02-150PC1 Datasheet - Page 7

• Manufacturer Part Number: M48Z02-150PC1
• Description: IC NVSRAM 16KBIT 150NS 24DIP
• Manufacturer: STMicroelectronics

Specifications of M48Z02-150PC1

• Format - Memory: RAM
• Memory Type: NVSRAM (Non-Volatile SRAM)
• Memory Size: 16K (2K x 8)
• Speed: 150ns
• Interface: Parallel
• Voltage - Supply: 4.75 V ~ 5.5 V
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 24-DIP (600 mil) Module
• Data Bus Width: 8 bit
• Organization: 2 Kb x 8
• Interface Type: Parallel
• Access Time: 150 ns
• Supply Voltage (max): 5.5 V
• Supply Voltage (min): 4.75 V
• Operating Current: 80 mA
• Maximum Operating Temperature: 70 C
• Minimum Operating Temperature: 0 C
• Mounting Style: Through Hole
• Capacitance, Input: 10 pF
• Capacitance, Output: 10 pF
• Current, Input, Leakage: ±1 μA
• Current, Operating: 80 mA
• Current, Output, Leakage: ±1
• Data Retention: 10 yrs.
• Density: 16K
• Package Type: PCDIP24
• Power Dissipation: 1 W
• Temperature, Operating: 0 to +70 °C
• Time, Access: 150 ns
• Time, Fall: ≤5 ns
• Time, Rise: ≤5 ns
• Voltage, Input, High: 5.05 to 5.8 V
• Voltage, Input, Low: 0.8 V
• Voltage, Output, High: 2.4 V
• Voltage, Output, Low: 0.4 V
• Voltage, Supply: 4.75 to 5.5 V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 497-2865-5

M48Z02, M48Z12
2
Note:
2.1
Operation modes
The M48Z02/12 also has its own power-fail detect circuit. The control circuitry constantly
monitors the single 5 V supply for an out of tolerance condition. When V
tolerance, the circuit write protects the SRAM, providing a high degree of data security in the
midst of unpredictable system operation brought on by low V
approximately 3 V, the control circuitry connects the battery which maintains data operation
until valid power returns.
Table 2.
1. See
X = V
READ mode
The M48Z02/12 is in the READ mode whenever W (WRITE enable) is high and E (chip
enable) is low. The device architecture allows ripple-through access of data from eight of
16,384 locations in the static storage array. Thus, the unique address specified by the 11
Address Inputs defines which one of the 2,048 bytes of data is to be accessed. Valid data
will be available at the data I/O pins within address access time (t
address input signal is stable, providing that the E and G access times are also satisfied. If
the E and G access times are not met, valid data will be available after the latter of the chip
enable access time (t
The state of the eight three-state data I/O signals is controlled by E and G. If the outputs are
activated before t
the address inputs are changed while E and G remain active, output data will remain valid
for output data hold time (t
Deselect
WRITE
READ
READ
Deselect
Deselect
Mode
IH
Table 10 on page 16
or V
IL
Operating modes
V
; V
SO
4.75 to 5.5 V
SO
4.5 to 5.5 V
to V
AVQV
≤ V
= battery backup switchover voltage.
V
PFD
or
SO
ELQV
CC
, the data lines will be driven to an indeterminate state until t
(1)
for details.
(min)
) or output enable access time (t
AXQX
(1)
Doc ID 2420 Rev 8
) but will go indeterminate until the next address access.
V
V
V
V
E
X
X
IH
IL
IL
IL
V
V
G
X
X
X
X
IH
IL
V
V
V
W
X
X
X
IH
IH
IL
GLQV
CC
High Z
High Z
High Z
High Z
D
DQ0-
DQ7
. As V
D
).
OUT
IN
AVQV
CC
) after the last
Battery backup mode
CC
falls below
Operation modes
CMOS standby
is out of
Standby
Power
Active
Active
Active
AVQV
. If
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