CY7C1347G-250AXC Cypress Semiconductor Corp, CY7C1347G-250AXC Datasheet - Page 16

• Manufacturer Part Number: CY7C1347G-250AXC
• Description: IC SRAM 4.5MBIT 250MHZ 100LQFP
• Manufacturer: Cypress Semiconductor Corp
• Type: Synchronousr

Specifications of CY7C1347G-250AXC

• Memory Size: 4.5M (128K x 36)
• Package / Case: 100-LQFP
• Format - Memory: RAM
• Memory Type: SRAM - Synchronous
• Speed: 250MHz
• Interface: Parallel
• Voltage - Supply: 3.15 V ~ 3.6 V
• Operating Temperature: 0°C ~ 70°C
• Access Time: 2.6 ns
• Maximum Clock Frequency: 250 MHz
• Supply Voltage (max): 3.6 V
• Supply Voltage (min): 3.135 V
• Maximum Operating Current: 325 mA
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Number Of Ports: 4
• Operating Supply Voltage: 3.3 V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

Switching Waveforms
Notes
Document #: 38-05516 Rev. *I
18. In this diagram, when CE is LOW, CE
19. Full width write can be initiated by either GW LOW, or by GW HIGH, BWE LOW, and BW
Data Out (Q)
Data In (D)
ADDRESS
BW[A :B]
ADSP
ADSC
BWE,
ADV
CLK
GW
OE
CE
BURST READ
High-Z
t ADS
t CES
t AS
A1
t ADH
t CEH
t AH
t CH
t
OEHZ
Byte write signals are
ignored for first cycle when
ADSP initiates burst
t CYC
(continued)
t ADS
1
t CL
t DS
is LOW, CE
Single WRITE
D(A1)
t ADH
t DH
2
is HIGH, and CE
A2
Figure 6. Write Cycle Timing
D(A2)
DON’T CARE
3
is LOW. When CE is HIGH, CE
D(A2 + 1)
t WES
BURST WRITE
t WEH
UNDEFINED
D(A2 + 1)
x
LOW.
ADV suspends burst
[18, 19]
D(A2 + 2)
1
ADSC extends burst
is HIGH, CE
D(A2 + 3)
2
is LOW, or CE
t ADS
A3
D(A3)
t ADH
t
ADVS
t WES
Extended BURST WRITE
3
D(A3 + 1)
is HIGH.
t
t WEH
ADVH
CY7C1347G
D(A3 + 2)
Page 16 of 24
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