CY7C1347G-133BGXC Cypress Semiconductor Corp, CY7C1347G-133BGXC Datasheet - Page 14

• Manufacturer Part Number: CY7C1347G-133BGXC
• Description: IC SRAM 4.5MBIT 133MHZ 119BGA
• Manufacturer: Cypress Semiconductor Corp
• Type: Synchronousr

Specifications of CY7C1347G-133BGXC

• Memory Size: 4.5M (128K x 36)
• Package / Case: 119-BGA
• Format - Memory: RAM
• Memory Type: SRAM - Synchronous
• Speed: 133MHz
• Interface: Parallel
• Voltage - Supply: 3.15 V ~ 3.6 V
• Operating Temperature: 0°C ~ 70°C
• Access Time: 4 ns
• Maximum Clock Frequency: 133 MHz
• Supply Voltage (max): 3.6 V
• Supply Voltage (min): 3.135 V
• Maximum Operating Current: 225 mA
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Number Of Ports: 4
• Operating Supply Voltage: 3.3 V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

Switching Characteristics
Over the Operating Range
Document #: 38-05516 Rev. *I
t
Clock
t
t
t
Output Times
t
t
t
t
t
t
t
Setup Times
t
t
t
t
t
t
Hold Times
t
t
t
t
t
t
Notes
POWER
CYC
CH
CL
CO
DOH
CLZ
CHZ
OEV
OELZ
OEHZ
AS
ADS
ADVS
WES
DS
CES
AH
ADH
ADVH
WEH
DH
CEH
11. Timing references level is 1.5 V when V
12. Test conditions shown in (a) of
13. This part has an internal voltage regulator; t
14. t
15. At any voltage and temperature, t
16. This parameter is sampled and not 100% tested.
Parameter
These specifications do not imply a bus contention condition, but reflect parameters guaranteed over worst case user conditions. Device is designed to achieve
High Z before Low Z under the same system conditions.
CHZ
, t
CLZ
, t
OELZ
V
Clock cycle time
Clock HIGH
Clock LOW
Data output valid after CLK rise
Data output hold after CLK rise
Clock to low Z
Clock to high Z
OE LOW to output valid
OE LOW to output low Z
OE HIGH to output high Z
Address setup before CLK rise
ADSC, ADSP setup before CLK rise
ADV setup before CLK rise
GW, BWE, BW
Data input setup before CLK rise
Chip enable setup before CLK rise
Address hold after CLK rise
ADSP, ADSC hold after CLK rise
ADV hold after CLK Rise
GW, BWE, BW
Data input hold after CLK rise
Chip enable hold after CLK rise
, and t
DD
(Typical) to the first Access
OEHZ
are specified with AC test conditions shown in part (b) of
[11, 12]
Figure 4 on page 13
OEHZ
[14, 15, 16]
Description
[14, 15, 16]
X
X
setup before CLK rise
hold after CLK rise
is less than t
DDQ
POWER
= 3.3 V and is 1.25 V when V
[14, 15, 16]
[14, 15, 16]
is the time that the power must be supplied above V
OELZ
unless otherwise noted.
[13]
and t
CHZ
is less than t
Min
1.7
4.0
1.7
1.0
1.2
1.2
1.2
1.2
1.2
1.2
0.3
0.3
0.3
0.3
0.3
0.3
DDQ
1
–
0
–
–
0
–
–250
= 2.5 V on all datasheets.
CLZ
Max
to eliminate bus contention between SRAMs when sharing the same data bus.
Figure 4 on page
2.6
2.6
2.6
2.6
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
Min
2.0
5.0
2.0
1.0
1.2
1.2
1.2
1.2
1.2
1.2
0.5
0.5
0.5
0.5
0.5
0.5
1
–
0
–
–
0
–
–200
DD
13. Transition is measured ±200 mV from steady-state voltage.
(min) initially before a read or write operation can be initiated.
Max
2.8
2.8
2.8
2.8
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
Min
6.0
2.5
2.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
0.5
0.5
0.5
0.5
0.5
0.5
1
–
0
–
–
0
–
–166
Max
3.5
3.5
3.5
3.5
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
Min
7.5
3.0
3.0
1.5
1.5
1.5
1.5
1.5
1.5
1.5
0.5
0.5
0.5
0.5
0.5
0.5
CY7C1347G
1
–
0
–
–
0
–
–133
Max
Page 14 of 24
4.0
4.0
4.5
4.0
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
Unit
ms
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
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