CY7C136-55JXC Cypress Semiconductor Corp, CY7C136-55JXC Datasheet - Page 4

• Manufacturer Part Number: CY7C136-55JXC
• Description: IC SRAM 16KBIT 55NS 52PLCC
• Manufacturer: Cypress Semiconductor Corp
• Type: Asynchronousr

Specifications of CY7C136-55JXC

• Memory Size: 16K (2K x 8)
• Package / Case: 52-PLCC
• Format - Memory: RAM
• Memory Type: SRAM - Dual Port, Asynchronous
• Speed: 55ns
• Interface: Parallel
• Voltage - Supply: 4.5 V ~ 5.5 V
• Operating Temperature: 0°C ~ 70°C
• Access Time: 55 ns
• Supply Voltage (max): 5.5 V
• Supply Voltage (min): 4.5 V
• Maximum Operating Current: 110 mA
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Number Of Ports: 2
• Operating Supply Voltage: 5 V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 428-2132; CY7C136-55JXC

Document #: 38-06031 Rev. *C
AC Test Loads and Waveforms
Switching Characteristics
Read Cycle
t
t
t
t
t
t
t
t
t
t
t
Write Cycle
t
t
t
t
t
t
t
t
t
t
Shaded areas contain preliminary information.
Notes:
10. Test conditions assume signal transition times of 5 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V and output loading of the specified
11. AC test conditions use V
12. At any given temperature and voltage condition for any given device, t
13. t
14. The internal write time of the memory is defined by the overlap of CE LOW and R/W LOW. Both signals must be LOW to initiate a write and either signal can
RC
AA
OHA
ACE
DOE
LZOE
HZOE
LZCE
HZCE
PU
PD
WC
SCE
AW
HA
SA
PWE
SD
HD
HZWE
LZWE
Parameter
I
terminate a write by going HIGH. The data input setup and hold timing should be referenced to the rising edge of the signal that terminates the write.
OL
LZCE
/I
Equivalent to:
OH,
OUTPUT
, t
LZWE
and 30-pF load capacitance.
INCLUDING
5V
[14]
, t
JIG AND
HZOE
SCOPE
Read Cycle Time
Address to Data Valid
Data Hold from Address Change
CE LOW to Data Valid
OE LOW to Data Valid
OE LOW to Low Z
OE HIGH to High Z
CE LOW to Low Z
CE HIGH to High Z
CE LOW to Power-Up
CE HIGH to Power-Down
Write Cycle Time
CE LOW to Write End
Address Set-up to Write End
Address Hold from Write End
Address Set-up to Write Start
R/W Pulse Width
Data Set-up to Write End
Data Hold from Write End
R/W LOW to High Z
R/W HIGH to Low Z
OUTPUT
30 pF
, t
LZOE,
OH
t
HZCE,
TH ÉVENIN EQUIVALENT
= 1.6V and V
R1 893Ω
(a)
and t
Description
R2
347Ω
250Ω
HZWE
Over the Operating Range (Speeds -15, -25, -30)
[9, 12]
[9, 12]
OL
[9, 12, 13]
[9, 12, 13]
[9]
[9]
= 1.4V.
are tested with C
[11]
[9]
[11]
[11]
[9]
1.4V
OUTPUT
INCLUDING
L
5V
= 5pF as in (b) of AC Test Loads. Transition is measured ±500 mV from steady-state voltage.
JIG AND
SCOPE
5 pF
HZCE
Min.
GND
is less than t
3.0V
7C136-15
15
15
12
12
12
10
0
3
3
0
2
0
0
0
7C146-15
R1 893Ω
(b)
< 5 ns
Max.
10%
LZCE
15
15
10
10
10
15
10
R2
347Ω
[3]
and t
ALL INPUT PULSES
90%
HZOE
Min.
25
25
20
20
15
15
7C132-25
0
3
5
0
2
0
0
0
7C136-25
7C142-25
7C146-25
[5, 10]
is less than t
Max.
25
25
15
15
15
25
15
[3]
(CY7C132/CY7C136 Only)
BUSY
CY7C132/CY7C136
CY7C142/CY7C146
LZOE
INT
OR
BUSY Output Load
90%
.
10%
Min.
30
30
25
25
25
15
< 5 ns
0
3
5
0
2
0
0
0
7C132-30
7C136-30
7C142-30
7C146-30
5V
281Ω
30 pF
Max.
30
30
20
15
15
25
15
Page 4 of 18
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
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