IS42S16160D-7TL ISSI, Integrated Silicon Solution Inc, IS42S16160D-7TL Datasheet - Page 20

• Manufacturer Part Number: IS42S16160D-7TL
• Description: IC SDRAM 256MBIT 143MHZ 54TSOP
• Manufacturer: ISSI, Integrated Silicon Solution Inc
• Type: SDRAMr

Specifications of IS42S16160D-7TL

• Package / Case: 54-TSOP II
• Memory Size: 256M (16Mx16)
• Format - Memory: RAM
• Memory Type: SDRAM
• Speed: 143MHz
• Interface: Parallel
• Voltage - Supply: 3 V ~ 3.6 V
• Operating Temperature: 0°C ~ 70°C
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 143 MHz
• Access Time: 6.5 ns, 5.4 ns
• Supply Voltage (max): 3.6 V
• Supply Voltage (min): 3 V
• Maximum Operating Current: 130 mA
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Organization: 16Mx16
• Density: 256Mb
• Address Bus: 15b
• Access Time (max): 6.5/5.4ns
• Maximum Clock Rate: 143MHz
• Operating Supply Voltage (typ): 3.3V
• Package Type: TSOP-II
• Operating Temp Range: 0C to 70C
• Operating Supply Voltage (max): 3.6V
• Operating Supply Voltage (min): 3V
• Supply Current: 130mA
• Pin Count: 54
• Mounting: Surface Mount
• Operating Temperature Classification: Commercial
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 706-1074; IS42S16160D-7TL

are registered on the positive edge of the clock signal,
CLK). Each of the 67,108,864-bit banks is organized as
IS42S83200D, IS42S16160D
FUNCTIONAL DESCRIPTION
The 256Mb SDRAMs are quad-bank DRAMs which operate
at 3.3V and include a synchronous interface (all signals
8,192 rows by 512 columns by 16 bits or 8,192 rows by
1,024 columns by 8 bits.
Read and write accesses to the SDRAM are burst oriented;
accesses start at a selected location and continue for
a programmed number of locations in a programmed
sequence. Accesses begin with the registration of an
ACTIVE command which is then followed by a READ or
WRITE command. The address bits registered coincident
with the ACTIVE command are used to select the bank
and row to be accessed (BA0 and BA1 select the bank, A0-
A12 select the row). The address bits A0-A9 (x8); A0-A8 (x16)
registered coincident with the READ or WRITE command
are used to select the starting column location for the
burst access.
Prior to normal operation, the SDRAM must be initial-
ized. The following sections provide detailed information
covering device initialization, register definition, command
descriptions and device operation.
20
Initialization
SDRAMs must be powered up and initialized in a
predefined manner.
The 256Mb SDRAM is initialized after the power is applied
to V
with DQM High and CKE High.
A 200µs delay is required prior to issuing any command
other than a COMMAND INHIBIT or a NOP.The COMMAND
INHIBIT or NOP may be applied during the 200us period and
should continue at least through the end of the period.
With at least one COMMAND INHIBIT or NOP command
having been applied, a PRECHARGE command should
be applied once the 200µs delay has been satisfied. All
banks must be precharged. This will leave all banks in an
idle state after which at least eight AUTO REFRESH cycles
must be performed. After the AUTO REFRESH cycles are
complete, the SDRAM is then ready for mode register
programming.
The mode register should be loaded prior to applying
any operational command because it will power up in an
unknown state.
dd
Integrated Silicon Solution, Inc. — www.issi.com
and V
ddq
(simultaneously) and the clock is stable
Rev. 00D
12/12/07