74LVX08MTC_Q Fairchild Semiconductor, 74LVX08MTC_Q Datasheet

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74LVX08MTC_Q

Manufacturer Part Number
74LVX08MTC_Q
Description
Logic Gates Qd 2-Input AND Gate
Manufacturer
Fairchild Semiconductor
Datasheet

Specifications of 74LVX08MTC_Q

Product
AND
Logic Family
74LVX
Number Of Gates
4
Number Of Lines (input / Output)
2 / 1
High Level Output Current
- 4 mA
Low Level Output Current
4 mA
Propagation Delay Time
14.9 ns, 10.6 ns
Supply Voltage - Max
3.6 V
Supply Voltage - Min
2 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Package / Case
TSSOP-14
Minimum Operating Temperature
- 40 C
Number Of Input Lines
2
Number Of Output Lines
1
©1993 Fairchild Semiconductor Corporation
74LVX08 Rev. 1.4.0
74LVX08
Low Voltage Quad 2-Input AND Gate
Features
Ordering Information
Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering number.
Connection Diagram
Pin Description
74LVX08M
74LVX08SJ
74LVX08MTC
A
O
n
Input voltage level translation from 5V to 3V
Ideal for low power/low noise 3.3V applications
Guaranteed simultaneous switching noise level and
dynamic threshold performance
n
, B
Number
All packages are lead free per JEDEC: J-STD-020B standard.
Pin Names
Order
n
Package
Number
MTC14
M14D
M14A
Outputs
Inputs
Description
14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow
14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
General Description
The LVX08 contains four 2-input AND gates. The inputs
tolerate voltages up to 7V allowing the interface of 5V
systems to 3V systems.
Logic Symbol
Package Description
IEEE/IEC
February 2008
www.fairchildsemi.com

Related parts for 74LVX08MTC_Q

74LVX08MTC_Q Summary of contents

Page 1

... B Inputs Outputs n ©1993 Fairchild Semiconductor Corporation 74LVX08 Rev. 1.4.0 General Description The LVX08 contains four 2-input AND gates. The inputs tolerate voltages allowing the interface of 5V systems to 3V systems. Package Description 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow 14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5 ...

Page 2

... Input Voltage I V Output Voltage O T Operating Temperature Input Rise and Fall Time Note: 1. Unused inputs must be held HIGH or LOW. They may not float. ©1993 Fairchild Semiconductor Corporation 74LVX08 Rev. 1.4.0 Parameter –0.5V I (1) Parameter 2 Rating –0.5V to +7.0V –20mA –0. –20mA +20mA – ...

Page 3

... Quiet Output Maximum Dynamic V OLP V Quiet Output Minimum Dynamic V OLV V Minimum HIGH Level Dynamic Input Voltage IHD V Maximum LOW Level Dynamic Input Voltage ILD Note: 2. Input t t 3ns r f ©1993 Fairchild Semiconductor Corporation 74LVX08 Rev. 1.4.0 V Conditions Min. Typ. Max. CC 2.0 3.0 3.6 2.0 3.0 3.6 2 ...

Page 4

... Input Capacitance IN C Power Dissipation Capacitance PD Note defined as the value of the internal equivalent capacitance which is calculated from the operating current PD consumption without load. Average operating current can be obtained by the eqation: I ©1993 Fairchild Semiconductor Corporation 74LVX08 Rev. 1.4 (V) C (pF) Min 2 3.3 ± ...

Page 5

... Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions, specifi ...

Page 6

... Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions, specifi ...

Page 7

... Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions, specifi ...

Page 8

... TRADEMARKS The following includes registered and unregistered trademarks and service marks, owned by Fairchild Semiconductor and/or its global subsidiaries, and is not intended exhaustive list of all such trademarks. ® ACEx Build it Now™ CorePLUS™ CROSSVOLT™ CTL™ Current Transfer Logic™ ...

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