MAX5941ACSE Maxim Integrated, MAX5941ACSE Datasheet - Page 5

• Manufacturer Part Number: MAX5941ACSE
• Description: Power Switch ICs - POE / LAN
• Manufacturer: Maxim Integrated

Note 1:
Note 2:
Note 3:
Note 4:
Note 5:
Note 6:
Note 7:
Note 8:
Note 9:
Note 10: PGOOD references to OUT while PGOOD references to V
Note 11: Guaranteed by design.
IEEE 802.3af-Compliant Power-Over-Ethernet
All min/max limits for the PD interface are production tested at +85°C (extended grade)/+70°C (commercial grade). Limits
at +25°C and -40°C are guaranteed by design. All PWM controller min/max limits are 100% production tested at +25°C
and +85°C (extended grade)/+70°C (commercial grade). Limits at -40°C are guaranteed by design, unless otherwise
noted.
The input offset current is illustrated in Figure 1.
Effective differential input resistance is defined as the differential resistance between GND and V
resistance.
Classification current is turned off whenever the IC is in power mode.
See Table 2 in the PD Classification Mode section. R
See Thermal Dissipation section for details.
When UVLO is connected to the midpoint of an external resistor-divider with a series resistance of 25.5kΩ (±1%), the turn-
on threshold set point for the power mode is defined by the external resistor-divider. Make sure the voltage on the UVLO
pin does not exceed its maximum rating of 8V when V
When the V
An input voltage or V
MAX5941A/MAX5941B to exit power-on mode (as long as the input voltage remains above an operable voltage level of 12V).
Interface/PWM Controller for Power Devices
_______________________________________________________________________________________
UVLO
is below V
UVLO
Figure 1. Effective Differential Input Resistance/Offset Current
TH, G, UVLO,
glitch below their respective thresholds shorter than or equal to t
I
OFFSET
I
INi
I
+1
INi
I
IN
the MAX5941 sets the turn-on voltage threshold internally (V
I
OFFSET
dR
i
≅
≅ I
(V
(I
INi
INi + 1
INi + 1
-
V
dR
INi
DISC
i
- V
- I
IN
INi
INi
V
)
is at the maximum voltage.
)
INi
=
and R
EE
(I
INi + 1
.
1V
1V
CL
- I
dR
INi
V
i
must be 100ppm or better.
INi
)
+1
OFF_DLY
UVLO,ON
EE
without any external
does not cause the
).
5