25LC640-I/SN Microchip Technology, 25LC640-I/SN Datasheet - Page 10

• Manufacturer Part Number: 25LC640-I/SN
• Description: IC EEPROM 64KBIT 2MHZ 8SOIC
• Manufacturer: Microchip Technology

Specifications of 25LC640-I/SN

• Memory Size: 64K (8K x 8)
• Package / Case: 8-SOIC (3.9mm Width)
• Operating Temperature: -40°C ~ 85°C
• Format - Memory: EEPROMs - Serial
• Memory Type: EEPROM
• Speed: 2MHz
• Interface: SPI, 3-Wire Serial
• Voltage - Supply: 2.5 V ~ 5.5 V
• Organization: 8 K x 8
• Interface Type: SPI
• Maximum Clock Frequency: 2 MHz
• Access Time: 230 ns
• Supply Voltage (max): 5.5 V
• Supply Voltage (min): 2.5 V
• Maximum Operating Current: 5 mA
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Operating Supply Voltage: 2.5 V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

25AA640/25LC640
3.5
The Read Status Register instruction (RDSR) provides
access to the STATUS register. The STATUS register
may be read at any time, even during a write cycle. The
STATUS register is formatted as follows:
The Write-In-Process (WIP) bit indicates whether the
25XX640 is busy with a write operation. When set to a
‘1’, a write is in progress, when set to a ‘0’, no write is
in progress. This bit is read-only.
FIGURE 3-6:
DS21223H-page 10
WPEN
SCK
SO
CS
7
SI
Read Status Register Instruction
(RDSR)
X
6
0
X
5
0
X
4
0
1
READ STATUS REGISTER TIMING SEQUENCE
High-Impedance
BP1
3
0
2
Instruction
BP0
0
2
3
0
WEL
4
1
1
5
WIP
0
0
6
1
7
The Write Enable Latch (WEL) bit indicates the status
of the write enable latch. When set to a ‘1’, the latch
allows writes to the array and STATUS register, when
set to a ‘0’, the latch prohibits writes to the array and
STATUS register. The state of this bit can always be
updated via the WREN or WRDI commands regardless
of the state of write protection on the STATUS register.
This bit is read-only.
The Block Protection (BP0 and BP1) bits indicate
which blocks are currently write-protected. These bits
are set by the user issuing the WRSR instruction. These
bits are nonvolatile.
See Figure 3-6 for RDSR timing sequence.
7
8
6
9
Data from STATUS Register
10
5
11
4
12
3
© 2008 Microchip Technology Inc.
13
2
14
1
15
0