25AA080D-I/MS Microchip Technology, 25AA080D-I/MS Datasheet - Page 11

• Manufacturer Part Number: 25AA080D-I/MS
• Description: IC SRL EEPROM 1KX8 1.8V 8-MSOP
• Manufacturer: Microchip Technology

Specifications of 25AA080D-I/MS

• Memory Size: 8K (1K x 8)
• Package / Case: 8-MSOP, Micro8™, 8-uMAX, 8-uSOP,
• Format - Memory: EEPROMs - Serial
• Memory Type: EEPROM
• Speed: 3MHZ, 5MHZ, 10MHZ
• Interface: SPI, 3-Wire Serial
• Voltage - Supply: 1.8 V ~ 5.5 V
• Operating Temperature: -40°C ~ 85°C
• Organization: 1 K x 8
• Interface Type: SPI
• Maximum Clock Frequency: 10 MHz
• Access Time: 160 ns
• Supply Voltage (max): 5.5 V
• Supply Voltage (min): 1.8 V
• Maximum Operating Current: 5 mA
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Operating Supply Voltage: 2.5 V, 3.3 V, 5 V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

2.6
The Write Status Register (WRSR) instruction allows the
user to write to the nonvolatile bits in the STATUS reg-
ister as shown in Table 2-2. The user is able to select
one of four levels of protection for the array by writing
to the appropriate bits in the STATUS register. The
array is divided up into four segments. The user has the
ability to write-protect none, one, two or all four of the
segments of the array. The partitioning is controlled as
shown in Table 2-3.
The Write-Protect Enable (WPEN) bit is also a
nonvolatile bit that is available as an enable bit for the WP
pin. The Write-Protect (WP) pin and the Write-Protect
Enable (WPEN) bit in the STATUS register control the
programmable hardware write-protect feature. Hardware
write protection is enabled when WP pin is low and the
WPEN bit is high. Hardware write protection is disabled
when either the WP pin is high or the WPEN bit is low.
When the chip is hardware write-protected, only writes to
nonvolatile bits in the STATUS register are disabled. See
Table 2-4 for a matrix of functionality on the WPEN bit.
FIGURE 2-7:
© 2009 Microchip Technology Inc.
SCK
CS
SO
SI
Write Status Register (WRSR)
Instruction
0
0
WRITE STATUS REGISTER TIMING SEQUENCE (WRSR)
0
1
0
Instruction
2
0
3
0
4
0
5
High-Impedance
0
6
1
7
See Figure 2-7 for the WRSR timing sequence.
TABLE 2-3:
7
8
BP1
0
0
1
1
6
9
Data to STATUS Register
10
5
11
4
ARRAY PROTECTION
BP0
0
1
0
1
25XX080C/D
12
3
13
2
Array Addresses
Write-Protected
(0300h-03FFh)
(0200h-03FFh)
(0000h-03FFh)
14
upper 1/4
upper 1/2
1
DS22151A-page 11
none
all
15
0