93LC86C-I/SN Microchip Technology, 93LC86C-I/SN Datasheet - Page 7

• Manufacturer Part Number: 93LC86C-I/SN
• Description: IC EEPROM 16KBIT 3MHZ 8SOIC
• Manufacturer: Microchip Technology

Specifications of 93LC86C-I/SN

• Memory Size: 16K (2K x 8 or 1K x 16)
• Package / Case: 8-SOIC (3.9mm Width)
• Operating Temperature: -40°C ~ 85°C
• Format - Memory: EEPROMs - Serial
• Memory Type: EEPROM
• Speed: 3MHz
• Interface: Microwire, 3-Wire Serial
• Voltage - Supply: 2.5 V ~ 5.5 V
• Organization: 2 K x 8 or 1 K x 16
• Interface Type: Microwire
• Maximum Clock Frequency: 3 MHz
• Supply Voltage (max): 5.5 V
• Supply Voltage (min): 2.5 V
• Maximum Operating Current: 3 mA
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Operating Supply Voltage: 2.5 V, 5.5 V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

2.4
The ERASE instruction forces all data bits of the
specified address to the logical ‘1’ state. The rising
edge of CLK before the last address bit initiates the
write cycle.
FIGURE 2-1:
2.5
The Erase All (ERAL) instruction will erase the entire
memory array to the logical ‘1’ state. The ERAL cycle
is identical to the erase cycle, except for the different
opcode. The ERAL cycle is completely self-timed. The
rising edge of CLK before the last data bit initiates the
write cycle. Clocking of the CLK pin is not necessary
after the device has entered the ERAL cycle.
FIGURE 2-2:
© 2008 Microchip Technology Inc.
CLK
CLK
DO
DO
CS
DI
CS
DI
Erase
Erase All (ERAL)
High-Z
High-Z
93AA86A/B/C, 93LC86A/B/C, 93C86A/B/C
1
1
ERASE TIMING
ERAL TIMING
1
0
1
0
A
1
N
A
0
N
-1 A
N
x
-2
•••
•••
A0
The DO pin indicates the Ready/
device if CS is brought high after a minimum of 250 ns
low (T
is still in progress. DO at logical ‘1’ indicates that the
register at the specified address has been erased and
the device is ready for another instruction.
The DO pin indicates the Ready/
device, if CS is brought high after a minimum of 250 ns
low (T
V
x
CC
Note:
Note:
T
T
must be ≥4.5V for proper operation of ERAL.
CSL
CSL
CSL
CSL
). DO at logical ‘0’ indicates that programming
).
T
After the Erase cycle is complete, issuing
a Start bit and then taking CS low will clear
the Ready/
After the ERAL command is complete,
issuing a Start bit and then taking CS low
will clear the Ready/
T
EC
WC
T
T
SV
SV
Check Status
Check Status
Busy
Busy
Busy
status from DO.
Ready
Ready
Busy
Busy
Busy
status from DO.
DS21797J-page 7
High-Z
High-Z
status of the
status of the
T
T
CZ
CZ