MR25H40MDFR Everspin Technologies, MR25H40MDFR Datasheet - Page 5

• Manufacturer Part Number: MR25H40MDFR
• Description: NVRAM 4Mb 3.3V 512Kx8 SPI Pre-Qual Sample MRAM
• Manufacturer: Everspin Technologies

Specifications of MR25H40MDFR

• Rohs: yes
• Data Bus Width: 8 bit
• Memory Size: 4 MB
• Organization: 512 K x 8
• Interface Type: SPI
• Supply Voltage - Max: 3.6 V
• Supply Voltage - Min: 3 V
• Operating Current: 20 mA
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Package / Case: DFN-8
• Maximum Power Dissipation: 0.6 W
• Operating Temperature Range: - 40 C to + 85 C
• Operating Voltage: 3 V to 3.6 V

Everspin Technologies © 2011
SPI COMMUNICATIONS PROTOCOL
WEL
Read Status Register (RDSR)
BP1
Block Protection
The Read Status Register (RDSR) command allows the Status Register to be read. The Status Register can
be read at any time to check the status of write enable latch bit, status register write protect bit, and block
write protect bits. For MR25H40, the write in progress bit (bit 0) is not written by the memory because
there is no write delay. The RDSR command is entered by driving CS low, sending the command code, and
then driving CS high.
The memory enters hardware block protection when the WP input is low and the Status Register Write Dis-
able (SRWD) bit is set to 0. The memory leaves hardware block protection only when the WP pin goes high.
While WP is low, the write protection blocks for the memory are determined by the status register bits BP0
and BP1 and cannot be modified without taking the WP signal high again.
If the WP signal is high (independent of the status of SRWD bit), the memory is in software protection
mode. This means that block write protection is controlled solely by the status register BP0 and BP1 block
write protect bits and this information can be modified using the WRSR command.
0
1
1
1
0
0
1
1
Status Register
SCK
CS
SO
SI
SRWD
X
0
1
1
BP0
0
1
0
1
0
0
WP
X
X
Low
High
0
1
0
High Impedance
2
Protected Area
None
Upper Quarter
Upper Half
All
Protected Blocks
Protected
Protected
Protected
Protected
Table 2.4 Block Memory Write Protection
0
3
Table 2.3 Memory Protection Modes
0
4
1
5
Figure 2.1 RDSR
0
6
1
7
MSB
5
MSB
7
Unprotected Blocks
Protected
Writable
Writable
Writable
0
Memory Contents
6
1
5
2
Status Register Out
Unprotected Area
All Memory
Lower Three-Quarters
Lower Half
None
4
3
3
4
2
5
MR25H40 Rev. 5, 11/2011
Status
Register
Protected
Writable
Protected
Writable
1
6
MR25H40
0
7
High Z
Mode 3
Mode 0