MAX9121EUE Maxim Integrated, MAX9121EUE Datasheet - Page 6

• Manufacturer Part Number: MAX9121EUE
• Description: LVDS Interface IC
• Manufacturer: Maxim Integrated

Specifications of MAX9121EUE

• Number Of Drivers: 4
• Number Of Receivers: 4
• Data Rate: 500 Mbps
• Operating Supply Voltage: 3 V to 3.6 V
• Maximum Power Dissipation: 755 mW
• Propagation Delay Time: 2.7 ns
• Supply Current: 25 uA

Quad LVDS Line Receivers with
Integrated Termination and Flow-Through Pinout
Table 1. Input/Output Function Table
The LVDS interface standard is a signaling method
intended for point-to-point communication over a con-
trolled-impedance medium as defined by the ANSI
TIA/EIA-644 and IEEE 1596.3 standards. The LVDS stan-
dard uses a lower voltage swing than other common
communication standards, achieving higher data rates
with reduced power consumption while reducing EMI
emissions and system susceptibility to noise.
The MAX9121/MAX9122 are 500Mbps, four-channel
LVDS receivers intended for high-speed, point-to-point,
low-power applications. Each channel accepts an
LVDS input and translates it to an LVTTL/LVCMOS out-
put. The receiver is capable of detecting differential
signals as low as 100mV and as high as 1V within an
input voltage range of 0 to 2.4V. The 250mV to 400mV
differential output of an LVDS driver is nominally cen-
tered around a +1.2V offset. This offset, coupled with
the receiver’s 0 to 2.4V input voltage range, allows an
approximate ±1V shift in the signal (as seen by the
receiver). This allows for a difference in ground refer-
6
10, 11, 14, 15
All other combinations of ENABLE pins
_______________________________________________________________________________________
1, 4, 5, 8
2, 3, 6, 7
9, 16
PIN
12
13
EN
H
ENABLES
EN, EN
NAME
OUT_
Detailed Description
IN_+
GND
V
IN_-
CC
L or open
EN
Inverting Differential Receiver Inputs
Noninverting Differential Receiver Inputs
Receiver Enable Inputs. When EN = high and EN = low or open, the outputs are active. For
other combinations of EN and EN, the outputs are disabled and in high impedance.
LVCMOS/LVTTL Receiver Outputs
Ground
Power-Supply Input. Bypass V
MAX9121
MAX9122
(IN_+) - (IN_-)
V
V
ences of the transmitter and the receiver, the common-
mode effects of coupled noise, or both. The LVDS stan-
dards specify an input voltage range of 0 to +2.4V
referenced to receiver ground.
The MAX9122 has an integrated termination resistor
that is internally connected across each receiver input.
The internal termination saves board space, eases lay-
out, and reduces stub length compared to an external
termination resistor. In other words, the transmission
line is terminated on the IC.
The fail-safe feature of the MAX9121/MAX9122 sets an
output high when:
• Inputs are open.
• Inputs are undriven and shorted.
• Inputs are undriven and terminated.
A fail-safe circuit is important because under these
conditions, noise at the inputs may switch the receiver
and it may appear to the system that data is being
CC
ID
ID
Don’t care
INPUTS
Open, undriven short, or undriven
100Ω parallel termination
Open or undriven short
≥
to GND with 0.1µF and 0.001µF ceramic capacitors.
≤ -100mV
+100mV
FUNCTION
Pin Description
OUTPUT
OUT_
H
H
Z
L
Fail-Safe