MAX9205EAI-T Maxim Integrated, MAX9205EAI-T Datasheet - Page 9

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MAX9205EAI-T

Manufacturer Part Number
MAX9205EAI-T
Description
LVDS Interface IC
Manufacturer
Maxim Integrated
Datasheet
Maxim Integrated
Figure 7. PLL Lock Time and PWRDN High-Impedance Delays
Figure 8. Serializer Delay
Figure 9. Definition of Deterministic Jitter (t
PWRDN
IN
TCLK
OUT±
OUT±
TCLK
TCLK_ R/F = HIGH
SYNC 1 = SYNC 2 = LOW
EN = HIGH
TCLK_R/F = HIGH
t
DJIT
SUPERIMPOSED RANDOM DATA
2.0V
IN0 - IN9 SYMBOL N
(OUT+) - (OUT-)
WAVEFORM
HIGH IMPEDANCE
1.5V
t
SD
START BIT
DJIT
V
t
DIFF
PL
)
TIMING SHOWN FOR TCLK_R/F = HIGH
= 0
OUT0 - OUT9 SYMBOL N
O DIFFERENTIAL
10-Bit Bus LVDS Serializers
IN0 - IN9 SYMBOL N + 1
1.5V
Figure 10. Definition of Random Jitter (t
t
ZH
OR t
t
RJIT
ZL
STOP BIT START BIT
MAX9205/MAX9207
V
DIFF
ACTIVE
= (OUT+) - (OUT-)
"CLOCK" PATTERN (1010...)
t
RJIT
OUT0 - OUT9 SYMBOL N+1
0.8V
t
HZ
OR t
RJIT
HIGH IMPEDANCE
LZ
)
(OUT+) - (OUT-)
WAVEFORM
STOP BIT
O DIFFERENTIAL
9

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