MAX9238EUM-D Maxim Integrated, MAX9238EUM-D Datasheet - Page 12

• Manufacturer Part Number: MAX9238EUM-D
• Description: LVDS Interface IC
• Manufacturer: Maxim Integrated

Hot-Swappable, 21-Bit, DC-Balanced LVDS
Deserializers
Keep the LVTTL/LVCMOS outputs and LVDS input sig-
nals separated to prevent crosstalk. A four-layer PC
board with separate layers for power, ground, LVDS
inputs, and digital signals is recommended.
The MAX9234/MAX9236/MAX9238 ESD tolerance is
rated for IEC 61000-4-2 Human Body Model and ISO
10605 standards. IEC 61000-4-2 and ISO 10605 specifiy
ESD tolerance for electronic systems. The Human Body
Model discharge components are C
1.5kΩ (Figure 12). For the Human Body Model, all pins
are rated for ±5kV contact discharge. The ISO 10605 dis-
charge components are C
(Figure 13). For ISO 10605, the LVDS outputs are rated
for ±8kV contact and ±25kV air discharge. The IEC
61000-4-2 discharge components are C
R
inputs are rated for ±8kV Contact Discharge and ±15kV
Air-Gap Discharge.
PWRDWN is 5V tolerant and is internally pulled down to
GND.
Skew margin (RSKM) is the time allowed for degrada-
tion of the serial data sampling setup and hold times by
sources other than the deserializer. The deserializer
sampling uncertainty is accounted for and does not
need to be subtracted from RSKM. The main outside
contributors of jitter and skew that subtract from RSKM
are interconnect intersymbol interference, serializer
pulse position uncertainty, and pair-to-pair path skew.
The outputs have a separate supply (V
to systems with 1.8V to 5V nominal input-logic levels. The
DC Electrical Characteristics table gives the maximum
supply current for V
switching frequencies with all outputs switching in the
worst-case switching pattern. The approximate incremen-
tal supply current for V
8pF load and worst-case pattern can be calculated using:
where:
I
C
tance.
V
f
MAX9234/MAX9236/MAX9238
V
12
I
C
I
D
T
= incremental supply current.
CCO
= incremental supply voltage.
= output clock-switching frequency.
= total internal (C
= 330Ω (Figure 14). For IEC 61000-4-2, the LVDS
Output Supply and Power Dissipation
I
I
= C
+ C
T
V
T
I
V
CCO
0.5f
INT
I
f
C
CCO
) and external (C
C
x 1 (clock output)
= 3.6V with 8pF load at several
x 21 (data outputs)
other than 3.6V with the same
S
Skew Margin (RSKM)
= 330pF and R
5V Tolerant Input
S
ESD Protection
CCO
= 100pF and R
Board Layout
L
S
) for interfacing
) load capaci-
= 150pF and
D
= 2kΩ
D
=
The incremental current is added to (for V
or subtracted from (for V
Characteristics table maximum supply current. The
internal output buffer capacitance is C
worst-case pattern-switching frequency of the data out-
puts is half the switching frequency of the output clock.
In the following example, the incremental supply current is
calculated for V
Figure 12. Human Body ESD Test Circuit
Figure 13. ISO 10605 Contact Discharge ESD Test Circuit
Figure 14. IEC 61000-4-2 Contact Discharge ESD Test Circuit
VOLTAGE
VOLTAGE
SOURCE
SOURCE
VOLTAGE
SOURCE
HIGH-
HIGH-
HIGH-
DC
DC
DC
C
T
CHARGE-CURRENT-
= C
CHARGE-CURRENT-
CHARGE-CURRENT-
LIMIT RESISTOR
LIMIT RESISTOR
LIMIT RESISTOR
CCO
50Ω TO 100Ω
V
INT
50Ω TO 100Ω
I
= 5.5V - 3.6V = 1.9V
1MΩ
= 5.5V, f
150pF
R1
100pF
330pF
+ C
R1
C
C
C
S
S
S
L
CCO
= 6pF + 8pF = 14pF
RESISTANCE
RESISTANCE
DISCHARGE
C
DISCHARGE
RESISTANCE
DISCHARGE
STORAGE
CAPACITOR
STORAGE
CAPACITOR
STORAGE
CAPACITOR
1.5kΩ
330Ω
= 34MHz, and C
2kΩ
R
R2
R2
< 3.6V) the DC Electrical
D
INT
Maxim Integrated
CCO
= 6pF. The
DEVICE
DEVICE
UNDER
UNDER
DEVICE
L
UNDER
TEST
TEST
TEST
= 8pF:
> 3.6V)