74HC4053D-Q100,118 NXP Semiconductors, 74HC4053D-Q100,118 Datasheet

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74HC4053D-Q100,118

Manufacturer Part Number
74HC4053D-Q100,118
Description
Encoders, Decoders, Multiplexers & Demultiplexers
Manufacturer
NXP Semiconductors
Datasheet
1.74HC4053PW-Q10011.pdf (30 pages)

Specifications of 74HC4053D-Q100,118

Rohs
yes
Product
Multiplexers / Demultiplexers
Logic Family
74HC
Propagation Delay Time
60 ns
Supply Voltage - Max
10 V
Supply Voltage - Min
2 V
Maximum Operating Temperature
+ 125 C
Mounting Style
SMD/SMT
Package / Case
SO-16
Minimum Operating Temperature
- 40 C
Operating Temperature Range
- 40 C to + 125 C
Operating Voltage
2 V to 10 V
Power Dissipation
500 mW
1. General description
2. Features and benefits
The 74HC4053-Q100; 74HCT4053-Q100 is a high-speed Si-gate CMOS device and is pin
compatible with Low-power Schottky TTL (LSTTL). It is specified in compliance with
JEDEC standard no. 7A.
The 74HC4053-Q100; 74HCT4053-Q100 is triple 2-channel analog
multiplexer/demultiplexer with a common enable input (E). Each multiplexer/demultiplexer
has two independent inputs/outputs (nY0 and nY1), a common input/output (nZ) and three
digital select inputs (Sn). With E LOW, one of the two switches is selected
(low-impedance ON-state) by S1 to S3. With E HIGH, all switches are in the
high-impedance OFF-state, independent of S1 to S3.
V
The V
74HCT4053-Q100. The analog inputs/outputs (nY0 to nY1, and nZ) can swing between
V
For operation as a digital multiplexer/demultiplexer, V
ground).
This product has been qualified to the Automotive Electronics Council (AEC) standard
Q100 (Grade 1) and is suitable for use in automotive applications.
CC
CC
74HC4053-Q100; 74HCT4053-Q100
Triple 2-channel analog multiplexer/demultiplexer
Rev. 2 — 22 November 2012
Automotive product qualification in accordance with AEC-Q100 (Grade 1)
Wide analog input voltage range from 5 V to +5 V
Low ON resistance:
Logic level translation: to enable 5 V logic to communicate with 5 V analog signals
Typical ‘break before make’ built-in
ESD protection:
Multiple package options
and GND are the supply voltage pins for the digital control inputs (S0 to S2, and E).
as a positive limit and V
CC
Specified from 40 C to +85 C and from 40 C to +125 C
80  (typical) at V
70  (typical) at V
60  (typical) at V
MIL-STD-883, method 3015 exceeds 2000 V
HBM JESD22-A114F exceeds 2000 V
MM JESD22-A115-A exceeds 200 V (C = 200 pF, R = 0 )
CDM AEC-Q100-011 revision B exceeds 1000 V
to GND ranges are 2.0 V to 10.0 V for 74HC4053-Q100, and 4.5 V to 5.5 V for
CC
CC
CC
 V
 V
 V
EE
as a negative limit. V
EE
EE
EE
= 4.5 V
= 6.0 V
= 9.0 V
CC
EE
 V
is connected to GND (typically
EE
may not exceed 10.0 V.
Product data sheet

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74HC4053D-Q100,118 Summary of contents

Page 1

Triple 2-channel analog multiplexer/demultiplexer Rev. 2 — 22 November 2012 1. General description The 74HC4053-Q100; 74HCT4053-Q100 is a high-speed Si-gate CMOS device and is pin compatible with Low-power Schottky TTL (LSTTL specified in compliance with JEDEC ...

Page 2

... Digital multiplexing and demultiplexing  Signal gating 4. Ordering information Table 1. Ordering information Type number Package Temperature range Name 40 C to +125 C 74HC4053D-Q100 74HCT4053D-Q100 40 C to +125 C 74HC4053PW-Q100 74HCT4053PW-Q100 40 C to +125 C 74HC4053BQ-Q100 74HCT4053BQ-Q100 74HC_HCT4053_Q100 Product data sheet 74HC4053-Q100; 74HCT4053-Q100 ...

Page 3

... NXP Semiconductors 5. Functional diagram Fig 1. Functional diagram Fig 2. Logic symbol 74HC_HCT4053_Q100 Product data sheet 74HC4053-Q100; 74HCT4053-Q100 Triple 2-channel analog multiplexer/demultiplexer LOGIC S1 11 LEVEL DECODER CONVERSION LOGIC S2 10 LEVEL CONVERSION LOGIC S3 9 LEVEL CONVERSION 8 7 GND ...

Page 4

... NXP Semiconductors from logic Fig 4. Schematic diagram (one switch) 6. Pinning information 6.1 Pinning 74HC4053-Q100 74HCT4053-Q100 1 2Y1 2 2Y0 3Y1 3Y0 GND 8 Fig 5. Pin configuration SO16 and TSSOP16 74HC_HCT4053_Q100 Product data sheet 74HC4053-Q100; 74HCT4053-Q100 Triple 2-channel analog multiplexer/demultiplexer ...

Page 5

... NXP Semiconductors 6.2 Pin description Table 2. Pin description Symbol Pin GND 8 S1, S2, S3 11, 10, 9 1Y0, 2Y0, 3Y0 12 1Y1, 2Y1, 3Y1 13 1Z, 2Z, 3Z 14, 15 Functional description [1] Table 3. Function table Inputs [ HIGH voltage level LOW voltage level don’t care. ...

Page 6

... NXP Semiconductors 9. Recommended operating conditions Table 5. Recommended operating conditions Symbol Parameter V supply voltage CC V input voltage I V switch voltage SW T ambient temperature amb t/V input transition rise and fall rate 10 V GND CC ( operating area Fig 7. ...

Page 7

... NXP Semiconductors 10. Static characteristics Table 6. R resistance per switch for 74HC4053-Q100 and 74HCT4053-Q100 for test circuit see the input voltage at a nYn or nZ terminal, whichever is assigned as an input the output voltage at a nYn or nZ terminal, whichever is assigned as an output. ...

Page 8

... NXP Semiconductors Table 6. R resistance per switch for 74HC4053-Q100 and 74HCT4053-Q100 for test circuit see the input voltage at a nYn or nZ terminal, whichever is assigned as an input the output voltage at a nYn or nZ terminal, whichever is assigned as an output. ...

Page 9

... NXP Semiconductors from select Sn input nYn GND V is  -------- - Fig 9. Test circuit for measuring R Table 7. Static characteristics for 74HC4053-Q100 Voltages are referenced to GND (ground = 0 V the input voltage at pins nYn or nZ, whichever is assigned as an input. ...

Page 10

... NXP Semiconductors Table 7. Static characteristics for 74HC4053-Q100 Voltages are referenced to GND (ground = 0 V the input voltage at pins nYn or nZ, whichever is assigned as an input the output voltage at pins nZ or nYn, whichever is assigned as an output. os Symbol Parameter I supply current CC C input capacitance ...

Page 11

... NXP Semiconductors Table 7. Static characteristics for 74HC4053-Q100 Voltages are referenced to GND (ground = 0 V the input voltage at pins nYn or nZ, whichever is assigned as an input the output voltage at pins nZ or nYn, whichever is assigned as an output. os Symbol Parameter I input leakage current I I OFF-state leakage ...

Page 12

... NXP Semiconductors Table 8. Static characteristics for 74HCT4053-Q100 Voltages are referenced to GND (ground = 0 V the input voltage at pins nYn or nZ, whichever is assigned as an input the output voltage at pins nZ or nYn, whichever is assigned as an output. os Symbol Parameter = 40 C to +85 C ...

Page 13

... NXP Semiconductors and and Fig 11. Test circuit for measuring OFF-state current and V = open-circuit and V = open-circuit Fig 12. Test circuit for measuring ON-state current 74HC_HCT4053_Q100 Product data sheet 74HC4053-Q100; 74HCT4053-Q100 Triple 2-channel analog multiplexer/demultiplexer ...

Page 14

... NXP Semiconductors 11. Dynamic characteristics Table 9. Dynamic characteristics for 74HC4053-Q100 GND = ns pF; for test circuit see the input voltage at a nYn or nZ terminal, whichever is assigned as an input the output voltage at a nYn or nZ terminal, whichever is assigned as an output. ...

Page 15

... NXP Semiconductors Table 9. Dynamic characteristics for 74HC4053-Q100 GND = ns pF; for test circuit see the input voltage at a nYn or nZ terminal, whichever is assigned as an input the output voltage at a nYn or nZ terminal, whichever is assigned as an output. ...

Page 16

... NXP Semiconductors Table 9. Dynamic characteristics for 74HC4053-Q100 GND = ns pF; for test circuit see the input voltage at a nYn or nZ terminal, whichever is assigned as an input the output voltage at a nYn or nZ terminal, whichever is assigned as an output. ...

Page 17

... NXP Semiconductors Table 10. Dynamic characteristics for 74HCT4053-Q100 GND = ns pF; for test circuit see the input voltage at a nYn or nZ terminal, whichever is assigned as an input the output voltage at a nYn or nZ terminal, whichever is assigned as an output. ...

Page 18

... NXP Semiconductors Table 10. Dynamic characteristics for 74HCT4053-Q100 GND = ns pF; for test circuit see the input voltage at a nYn or nZ terminal, whichever is assigned as an input the output voltage at a nYn or nZ terminal, whichever is assigned as an output. ...

Page 19

... NXP Semiconductors E, Sn inputs For 74HC4053-Q100 For 74HCT4053-Q100 Fig 14. Turn-on and turn-off times Definitions for test circuit; see R = termination resistance should be equal to the output impedance load capacitance including jig and probe capacitance load resistance Test selection switch. ...

Page 20

... NXP Semiconductors Table 11. Test data Test Input PHL PLH [ PZH PHZ [ PZL PLZ [ ns; when measuring max [2] V values For 74HC4053-Q100 For 74HCT4053-Q100 11.1 Additional dynamic characteristics Table 12. Additional dynamic characteristics Recommended conditions and typical values ...

Page 21

... NXP Semiconductors Fig 16. Test circuit for measuring sine-wave distortion V = 4.5 V; GND = Test circuit 0 iso (dB 100 10 b. Isolation (OFF-state function of frequency Fig 17. Test circuit for measuring isolation (OFF-state) 74HC_HCT4053_Q100 Product data sheet 74HC4053-Q100; 74HCT4053-Q100 Triple 2-channel analog multiplexer/demultiplexer ...

Page 22

... NXP Semiconductors Fig 18. Test circuits for measuring crosstalk between any two switches/multiplexers G Fig 19. Test circuit for measuring crosstalk between control input and any switch 74HC_HCT4053_Q100 Product data sheet 74HC4053-Q100; 74HCT4053-Q100 Triple 2-channel analog multiplexer/demultiplexer 0 nYn/nZ nZ/nYn GND ...

Page 23

... NXP Semiconductors V = 4.5 V; GND = Test circuit (dB Typical frequency response Fig 20. Test circuit for frequency response 74HC_HCT4053_Q100 Product data sheet 74HC4053-Q100; 74HCT4053-Q100 Triple 2-channel analog multiplexer/demultiplexer nYn/nZ nZ/nYn GND EE = 4  k ...

Page 24

... NXP Semiconductors 12. Package outline SO16: plastic small outline package; 16 leads; body width 3 pin 1 index 1 DIMENSIONS (inch dimensions are derived from the original mm dimensions UNIT max. 0.25 1.45 mm 1.75 0.25 0.10 1.25 0.010 0.057 inches 0.069 0.01 0.004 0.049 Note 1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included. ...

Page 25

... NXP Semiconductors TSSOP16: plastic thin shrink small outline package; 16 leads; body width 4 pin 1 index 1 DIMENSIONS (mm are the original dimensions) A UNIT max. 0.15 0.95 mm 1.1 0.25 0.05 0.80 Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic interlead protrusions of 0.25 mm maximum per side are not included. ...

Page 26

... NXP Semiconductors DHVQFN16: plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads; 16 terminals; body 2.5 x 3.5 x 0.85 mm terminal 1 index area terminal 1 index area DIMENSIONS (mm are the original dimensions) (1) A UNIT max. 0.05 0. 0.2 0.00 0.18 Note 1. Plastic or metal protrusions of 0.075 mm maximum per side are not included. ...

Page 27

... NXP Semiconductors 13. Abbreviations Table 13. Abbreviations Acronym Description CMOS Complementary Metal-Oxide Semiconductor ESD ElectroStatic Discharge HBM Human Body Model MM Machine Model MIL Military 14. Revision history Table 14. Revision history Document ID Release date 74HC_HCT4053_Q100 v.2 20121122 Modifications: 74HC_HCT4053_Q100 v.1 20120720 74HC_HCT4053_Q100 Product data sheet 74HC4053-Q100; 74HCT4053-Q100 ...

Page 28

... Terms and conditions of commercial sale of NXP Semiconductors. Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice ...

Page 29

... NXP Semiconductors No offer to sell or license — Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. Export control — This document as well as the item(s) described herein may be subject to export control regulations ...

Page 30

... NXP Semiconductors 17. Contents 1 General description . . . . . . . . . . . . . . . . . . . . . . 1 2 Features and benefits . . . . . . . . . . . . . . . . . . . . 1 3 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 4 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 5 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 3 6 Pinning information . . . . . . . . . . . . . . . . . . . . . . 4 6.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 6.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 5 7 Functional description . . . . . . . . . . . . . . . . . . . 5 8 Limiting values Recommended operating conditions Static characteristics Dynamic characteristics . . . . . . . . . . . . . . . . . 14 11.1 Additional dynamic characteristics . . . . . . . . . 20 12 Package outline ...

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