74LVCH32374AEC/G NXP Semiconductors, 74LVCH32374AEC/G Datasheet

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74LVCH32374AEC/G

Manufacturer Part Number
74LVCH32374AEC/G
Description
Buffers & Line Drivers 32-BIT 5V TOLERANT
Manufacturer
NXP Semiconductors
Datasheet

Specifications of 74LVCH32374AEC/G

Product Category
Buffers & Line Drivers
Rohs
yes
Factory Pack Quantity
285
Part # Aliases
74LVCH32374AEC/G-S

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
74LVCH32374AEC/G,5
Manufacturer:
NXP Semiconductors
Quantity:
10 000
Part Number:
74LVCH32374AEC/G:5
Manufacturer:
NXP Semiconductors
Quantity:
10 000
1. General description
2. Features and benefits
The 74LVCH32374A is a 32-bit edge-triggered flip-flop featuring separate D-type inputs
for each flip-flop and 3-state outputs for bus oriented applications. The device consists of
4 sections of 8 edge-triggered flip-flops. A clock (pin nCP) input and an output enable
input (pin nOE) are provided per 8-bit section. The flip-flops will store the state of their
individual D-inputs that meet the set-up and hold time requirements on the LOW-to-HIGH
nCP transition. When pin nOE is LOW, the contents of the flip-flops are available at the
outputs. When pin nOE is HIGH, the outputs go to the high-impedance OFF-state.
Operation of pin nOE does not affect the state of the flip-flops. The inputs can be driven
from either 3.3 V or 5 V devices. In 3-state operation, the outputs can handle 5 V. These
features allow the use of these devices in a mixed 3.3 V or 5 V environment.
Bus hold on data inputs eliminates the need for external pull-up resistors to hold unused
inputs.
74LVCH32374A
32-bit edge-triggered D-type flip-flop with 5 V tolerant
inputs/outputs; 3-state
Rev. 3 — 18 December 2012
5 V tolerant inputs/outputs for interfacing with 5 V logic
Wide supply voltage range from 1.2 V to 3.6 V
CMOS low power consumption
Multibyte flow-through standard pin-out architecture
Multiple low inductance supply pins for minimum noise and ground bounce
Direct interface with TTL levels
All data inputs have bus hold
High impedance when V
Latch-up performance exceeds 500 mA per JESD 78 Class II
Complies with JEDEC standard:
ESD protection:
Specified from 40 C to +85 C and 40 C to +125 C
Packaged in plastic fine-pitch ball grid array package
JESD8-7A (1.65 V to 1.95 V)
JESD8-5A (2.3 V to 2.7 V)
JESD8-C/JESD36 (2.7 V to 3.6 V)
HBM JESD22-A114F exceeds 2000 V
MM JESD22-A115-B exceeds 200 V
CDM JESD22-C101E exceeds 1000 V
CC
= 0 V
Product data sheet

Related parts for 74LVCH32374AEC/G

74LVCH32374AEC/G Summary of contents

Page 1

D-type flip-flop with 5 V tolerant inputs/outputs; 3-state Rev. 3 — 18 December 2012 1. General description The 74LVCH32374A is a 32-bit edge-triggered flip-flop featuring separate D-type inputs for each flip-flop and 3-state outputs for bus oriented ...

Page 2

... NXP Semiconductors 3. Ordering information Table 1. Ordering information Type number Package Temperature range 74LVCH32374AEC 40 C to +125 C 4. Functional diagram 1D0 1CP 1OE 3D0 3CP 3OE Fig 1. Logic symbol Fig 2. Bus hold circuit 74LVCH32374A Product data sheet 32-bit edge-triggered D-type flip-flop tolerant; 3-state ...

Page 3

... NXP Semiconductors 5. Pinning information 5.1 Pinning 6 1D1 1D3 1D5 1D7 2D1 2D3 2D5 2D6 3D1 3D3 3D5 3D7 4D1 4D3 4D5 4D6 5 1D0 1D2 1D4 1D6 2D0 2D2 2D4 2D7 3D0 3D2 3D4 3D6 4D0 4D2 4D4 4D7 4 1CP GND 3 1OE GND ...

Page 4

... NXP Semiconductors 6. Functional description [1] Table 3. Function table Operating mode Input nOE Load and read L register L Load register and H disable outputs H [ HIGH voltage level L = LOW voltage level h = HIGH voltage level one set-up time prior to the HIGH-to-LOW CP transition l = LOW voltage level one set-up time prior to the HIGH-to-LOW CP transition Z = high-impedance OFF-state  ...

Page 5

... NXP Semiconductors 8. Recommended operating conditions Table 5. Recommended operating conditions Symbol Parameter V supply voltage CC V input voltage I V output voltage O T ambient temperature amb t/V input transition rise and fall rate 9. Static characteristics Table 6. Static characteristics At recommended operating conditions. Voltages are referenced to GND (ground = 0 V). ...

Page 6

... NXP Semiconductors Table 6. Static characteristics At recommended operating conditions. Voltages are referenced to GND (ground = 0 V). Symbol Parameter Conditions I OFF-state output current GND O I power-off OFF CC leakage current I supply current I additional per input pin; ...

Page 7

... NXP Semiconductors 10. Dynamic characteristics Table 7. Dynamic characteristics Voltages are referenced to GND (ground = 0 V). For test circuit see Symbol Parameter Conditions t propagation nCP to nQn; see pd delay enable time nOE to nQn; see disable time nOE to nQn ...

Page 8

... NXP Semiconductors Table 7. Dynamic characteristics Voltages are referenced to GND (ground = 0 V). For test circuit see Symbol Parameter Conditions f maximum see Figure 4 max frequency output skew 3.6 V sk(o) CC time C power per input dissipation V CC capacitance ...

Page 9

... NXP Semiconductors nCP input nDn input nQn output Measurement points are given in V and V are typical output voltage levels that occur with the output load Fig 5. Set-up and hold times for inputs (nDn) to inputs (nCP) nOE input output LOW-to-OFF ...

Page 10

... NXP Semiconductors Table 8. Measurement points Supply voltage Input 2.7 V 2 3.6 V 2.7 V Test data is given in Table R = Load resistance Load capacitance including jig and probe capacitance Termination resistance should be equal to the output impedance Z T Fig 7 ...

Page 11

... NXP Semiconductors 12. Package outline LFBGA96: plastic low profile fine-pitch ball grid array package; 96 balls; body 13.5 x 5.5 x 1.05 mm ball A1 index area ball A1 index area DIMENSIONS (mm are the original dimensions) A UNIT max. 0.41 1.2 0.51 mm 1.5 0.31 0.9 0.41 OUTLINE VERSION ...

Page 12

... Revision history Document ID Release date 74LVCH32374A v.3 20121218 • Modifications: The format of this data sheet has been redesigned to comply with the new identity guidelines of NXP Semiconductors. • Legal texts have been adapted to the new company name where appropriate. • Table ranges. 74LVCH32374A v.2 20040519 74LVCH32374A v ...

Page 13

... Terms and conditions of commercial sale of NXP Semiconductors. Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice ...

Page 14

... D-type flip-flop tolerant; 3-state NXP Semiconductors’ specifications such use shall be solely at customer’s own risk, and (c) customer fully indemnifies NXP Semiconductors for any liability, damages or failed product claims resulting from customer design and use of the product for automotive applications beyond NXP Semiconductors’ ...

Page 15

... NXP Semiconductors 17. Contents 1 General description . . . . . . . . . . . . . . . . . . . . . . 1 2 Features and benefits . . . . . . . . . . . . . . . . . . . . 1 3 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 4 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2 5 Pinning information . . . . . . . . . . . . . . . . . . . . . . 3 5.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 5.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 3 6 Functional description . . . . . . . . . . . . . . . . . . . 4 7 Limiting values Recommended operating conditions Static characteristics Dynamic characteristics . . . . . . . . . . . . . . . . . . 7 11 Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 12 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 11 13 Abbreviations ...

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