74AHCT125D-Q100,11 NXP Semiconductors, 74AHCT125D-Q100,11 Datasheet

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74AHCT125D-Q100,11

Manufacturer Part Number
74AHCT125D-Q100,11
Description
Buffers & Line Drivers
Manufacturer
NXP Semiconductors
Datasheet

Specifications of 74AHCT125D-Q100,11

Rohs
yes
Number Of Input Lines
4
Number Of Output Lines
4
Polarity
Non-Inverting
Supply Voltage - Max
5.5 V
Supply Voltage - Min
4.5 V
Maximum Operating Temperature
+ 125 C
Mounting Style
SMD/SMT
Package / Case
SO-14
Logic Family
74AHCT
Logic Type
CMOS
Maximum Power Dissipation
500 mW
Minimum Operating Temperature
- 40 C
Output Type
3-State
Propagation Delay Time
11.5 ns
Supply Current
75 mA
1. General description
2. Features and benefits
The 74AHC125-Q100; 74AHCT125-Q100 is a high-speed Si-gate CMOS device and is
pin compatible with Low-power Schottky TTL (LSTTL). They are specified in compliance
with JEDEC standard JESD7-A.
The 74AHC125-Q100; 74AHCT125-Q100 provides four non-inverting buffer/line drivers
with 3-state outputs. The 3-state outputs (nY) are controlled by the output enable input
(nOE). A HIGH at nOE causes the outputs to assume a high-impedance OFF-state.
The 74AHC125-Q100; 74AHCT125-Q100 is identical to the 74AHC126-Q100;
74AHCT126-Q100 but has active LOW enable inputs.
This product has been qualified to the Automotive Electronics Council (AEC) standard
Q100 (Grade 1) and is suitable for use in automotive applications.
74AHC125-Q100;
74AHCT125-Q100
Quad buffer/line driver; 3-state
Rev. 1 — 5 June 2012
Automotive product qualification in accordance with AEC-Q100 (Grade 1)
Balanced propagation delays
All inputs have a Schmitt trigger action
Inputs accept voltages higher than V
For 74AHC125-Q100: CMOS input levels
For 74AHCT125-Q100: TTL input levels
ESD protection:
Multiple package options
Specified from 40 C to +85 C and from 40 C to +125 C
MIL-STD-883, method 3015 exceeds 2000 V
HBM JESD22-A114F exceeds 2000 V
MM JESD22-A115-A exceeds 200 V (C = 200 pf, R = 0 )
CC
Product data sheet

Related parts for 74AHCT125D-Q100,11

74AHCT125D-Q100,11 Summary of contents

Page 1

... Low-power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard JESD7-A. The 74AHC125-Q100; 74AHCT125-Q100 provides four non-inverting buffer/line drivers with 3-state outputs. The 3-state outputs (nY) are controlled by the output enable input (nOE). A HIGH at nOE causes the outputs to assume a high-impedance OFF-state. ...

Page 2

... NXP Semiconductors 3. Ordering information Table 1. Ordering information Type number Package Temperature range Name 40 C to +125 C 74AHC125D-Q100 74AHCT125D-Q100 40 C to +125 C 74AHC125PW-Q100 74AHCT125PW-Q100 40 C to +125 C 74AHC125BQ-Q100 74AHCT125BQ-Q100 4. Functional diagram 1OE 2OE ...

Page 3

... NXP Semiconductors 5. Pinning information 5.1 Pinning 74AHC125-Q100 74AHCT125-Q100 1OE 2OE GND 7 Fig 4. Pin configuration SO14 and TSSOP14 5.2 Pin description Table 2. Pin description Symbol Pin 1OE, 2OE, 3OE, 4OE 1, 4, 10, 13 1A, 2A, 3A 1Y, 2Y, 3Y ...

Page 4

... NXP Semiconductors 7. Limiting values Table 4. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V). Symbol Parameter V supply voltage CC V input voltage I I input clamping current IK I output clamping current OK I output current O I supply current ...

Page 5

... NXP Semiconductors 9. Static characteristics Table 6. Static characteristics Voltages are referenced to GND (ground = 0 V). Symbol Parameter Conditions 74AHC125-Q100 V HIGH-level input voltage LOW-level input voltage HIGH-level output voltage = 50   ...

Page 6

... NXP Semiconductors Table 6. Static characteristics Voltages are referenced to GND (ground = 0 V). Symbol Parameter Conditions 74AHCT125-Q100 V HIGH-level input voltage V LOW-level input voltage V HIGH-level output voltage = 50  8 LOW-level output voltage = 50  ...

Page 7

... NXP Semiconductors 10. Dynamic characteristics Table 7. Dynamic characteristics GND = 0 V; For test circuit see Figure Symbol Parameter Conditions 74AHC125-Q100 t propagation nA to nY; see pd delay enable time nOE to nY; see 3 3.6 V ...

Page 8

... NXP Semiconductors Table 7. Dynamic characteristics GND = 0 V; For test circuit see Figure Symbol Parameter Conditions 74AHCT125-Q100 t propagation nA to nY; see pd delay enable time nOE to nY; see 4 5 disable time nOE to nY; see ...

Page 9

... NXP Semiconductors nOE input output LOW-to-OFF OFF-to-LOW output HIGH-to-OFF OFF-to-HIGH Measurement points are given in V and V are typical voltage output levels that occur with the output load Fig 7. Enable and disable times Table 8. Measurement points Type ...

Page 10

... NXP Semiconductors negative Test data is given in Table Definitions test circuit Termination resistance should be equal to output impedance Load capacitance including jig and probe capacitance Load resistance Test selection switch. Fig 8. Test circuit for measuring switching times Table 9. Test data ...

Page 11

... NXP Semiconductors 12. Package outline SO14: plastic small outline package; 14 leads; body width 3 pin 1 index 1 e DIMENSIONS (inch dimensions are derived from the original mm dimensions) A UNIT max. 0.25 1.45 mm 1.75 0.25 0.10 1.25 0.010 0.057 inches 0.069 0.01 0.004 0.049 Note 1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included. ...

Page 12

... NXP Semiconductors TSSOP14: plastic thin shrink small outline package; 14 leads; body width 4 pin 1 index 1 e DIMENSIONS (mm are the original dimensions) A UNIT max. 0.15 0.95 mm 1.1 0.25 0.05 0.80 Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic interlead protrusions of 0.25 mm maximum per side are not included. ...

Page 13

... NXP Semiconductors DHVQFN14: plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads; 14 terminals; body 2 0.85 mm terminal 1 index area terminal 1 index area DIMENSIONS (mm are the original dimensions) (1) A UNIT max. 0.05 0. 0.2 0.00 0.18 Note 1. Plastic or metal protrusions of 0.075 mm maximum per side are not included. ...

Page 14

... NXP Semiconductors 13. Abbreviations Table 10. Abbreviations Acronym Description CMOS Complementary Metal Oxide Semiconductor LSTTL Low-power Schottky Transistor-Transistor Logic ESD ElectroStatic Discharge HBM Human Body Model MM Machine Model CDM Charge-Device Model TTL Transistor-Transistor Logic MIL Military 14. Revision history Table 11. Revision history Document ID Release date 74AHC_AHCT125_Q100 v ...

Page 15

... Terms and conditions of commercial sale of NXP Semiconductors. Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice ...

Page 16

... NXP Semiconductors No offer to sell or license — Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. Export control — This document as well as the item(s) described herein may be subject to export control regulations ...

Page 17

... NXP Semiconductors 17. Contents 1 General description . . . . . . . . . . . . . . . . . . . . . . 1 2 Features and benefits . . . . . . . . . . . . . . . . . . . . 1 3 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 4 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2 5 Pinning information . . . . . . . . . . . . . . . . . . . . . . 3 5.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 5.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 3 6 Functional description . . . . . . . . . . . . . . . . . . . 3 7 Limiting values Recommended operating conditions Static characteristics Dynamic characteristics . . . . . . . . . . . . . . . . . . 7 11 Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 12 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 11 13 Abbreviations ...

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