MAX6618AUB+G126 Maxim Integrated, MAX6618AUB+G126 Datasheet - Page 13

• Manufacturer Part Number: MAX6618AUB+G126
• Description: Interface - Specialized PECI-to-I2C Translator
• Manufacturer: Maxim Integrated
• Series: MAX6618r

Specifications of MAX6618AUB+G126

• Part # Aliases: 90-66180+G16

The MAX6618 SCL and SDA lines operate as both
inputs and open-drain outputs. A pullup resistor is
required on SCL and SDA.
Each transmission consists of a START condition sent
by a master, followed by the MAX6618 7-bit slave
address, plus an R/W bit, one or more data bytes, and
finally a STOP condition (Figure 6). To write to a
MAX6618 register, a write transmission consists of a
START condition, followed by the MAX6618 7-bit slave
address plus R/W = 0, a register address byte, one
data byte, and finally a STOP condition. To read from a
MAX6618 register, a combined write and read trans-
missions are required. The first write transmission con-
sists of a START condition, followed by the MAX6618
7-bit slave address plus R/W = 0, a register address
byte, and finally a STOP condition that sets the register
to be read. The second read transmission consists of a
START condition, followed by the MAX6618 7-bit slave
address plus R/W = 1, one or more data bytes, and
Figure 6. Start and Stop Conditions
SDA
SCL
CONDITION
START
S
______________________________________________________________________________________
CONDITION
STOP
P
finally a STOP condition that reads the data from the
specified register. These write and read transmissions
can be joined using a repeated START even though the
MAX6618 7-bit slave address needs to be present pre-
ceding the R/W bits.
Both SCL and SDA remain high when the interface is
not busy. A master signals the beginning of a transmis-
sion with a START (S) condition by transitioning SDA
from high to low while SCL is high. When the master
has finished communicating with the slave, it issues a
STOP (P) condition by transitioning SDA from low to
high while SCL is high. The bus is then free for another
transmission (Figure 6).
One data bit is transferred during each clock pulse.
The data on SDA must remain stable while SCL is high
(Figure 7).
Figure 7. Bit Transfer
PECI-to-I
SDA
SCL
DATA LINE STABLE;
DATA VALID
Data Transfer and Acknowledge
CHANGE OF DATA
2
ALLOWED
C Translator
Start and Stop Conditions
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