C8051F997-GUR Silicon Labs, C8051F997-GUR Datasheet - Page 209

• Manufacturer Part Number: C8051F997-GUR
• Description: 8-bit Microcontrollers - MCU 8kB 14-CH CDC
• Manufacturer: Silicon Labs

Specifications of C8051F997-GUR

• Rohs: yes
• Core: 8051
• Processor Series: C8051
• Data Bus Width: 8 bit

Internal Register Definition 20.4. RTC0CN: SmaRTClock Control
SmaRTClock Address = 0x04
Note: The ALRM flag will remain asserted for a maximum of one SmaRTClock cycle. See Section “Power
Name
Reset
Type
Bit
7
6
5
4
3
2
1
0
Bit
Management” on page 161 for information on how to capture a SmaRTClock Alarm event using a flag which
is not automatically cleared by hardware.
RTC0AEN SmaRTClock Alarm Enable.
RTC0CAP SmaRTClock Timer Capture.
RTC0SET
MCLKEN
OSCFAIL
RTC0EN
RTC0TR
Name
ALRM
RTC0EN
R/W
7
0
SmaRTClock Enable.
Enables/disables the SmaRTClock oscillator and associated bias currents.
0: SmaRTClock oscillator disabled.
1: SmaRTClock oscillator enabled.
Missing SmaRTClock Detector Enable.
Enables/disables the missing SmaRTClock detector.
0: Missing SmaRTClock detector disabled.
1: Missing SmaRTClock detector enabled.
SmaRTClock Oscillator Fail Event Flag.
Set by hardware when a missing SmaRTClock detector timeout occurs. Must be cleared by
software. The value of this bit is not defined when the SmaRTClock 
oscillator is disabled.
SmaRTClock Timer Run Control.
Controls if the SmaRTClock timer is running or stopped (holds current value).
0: SmaRTClock timer is stopped.
1: SmaRTClock timer is running.
Enables/disables the SmaRTClock alarm function. Also clears the ALRM flag.
0: SmaRTClock alarm disabled.
1: SmaRTClock alarm enabled.
SmaRTClock Alarm Event
Flag and Auto Reset Enable.
Reads return the state of the
alarm event flag.
Writes enable/disable the 
Auto Reset function.
SmaRTClock Timer Set.
Writing 1 initiates a SmaRTClock timer set operation. This bit is cleared to 0 by hardware to indi-
cate that the timer set operation is complete.
Writing 1 initiates a SmaRTClock timer capture operation. This bit is cleared to 0 by hardware to
indicate that the timer capture operation is complete.
MCLKEN
R/W
6
0
OSCFAIL
Varies
R/W
5
RTC0TR
R/W
Rev. 1.1
Read:
0: SmaRTClock alarm event
flag is de-asserted.
1: SmaRTClock alarm event
flag is asserted.
4
0
C8051F99x-C8051F98x
Function
RTC0AEN
R/W
3
0
ALRM
R/W
2
0
Write:
0: Disable Auto Reset.
1: Enable Auto Reset.
RTC0SET RTC0CAP
R/W
1
0
R/W
0
0
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