C8051F562-IMR Silicon Labs, C8051F562-IMR Datasheet - Page 235

• Manufacturer Part Number: C8051F562-IMR
• Description: 8-bit Microcontrollers - MCU 50 MIPS 32 kB 2 kB LIN 2.1 SPI
• Manufacturer: Silicon Labs

Specifications of C8051F562-IMR

• Rohs: yes
• Core: 8051
• Processor Series: C8051
• Data Bus Width: 8 bit

23.2. Data Format
UART0 has a number of available options for data formatting. Data transfers begin with a start bit (logic
low), followed by the data bits (sent LSB-first), a parity or extra bit (if selected), and end with one or two
stop bits (logic high). The data length is variable between 5 and 8 bits. A parity bit can be appended to the
data, and automatically generated and detected by hardware for even, odd, mark, or space parity. The stop
bit length is selectable between 1 and 2 bit times, and a multi-processor communication mode is available
for implementing networked UART buses. All of the data formatting options can be configured using the
SMOD0 register, shown in SFR Definition 23.2. Figure 23.2 shows the timing for a UART0 transaction
without parity or an extra bit enabled. Figure 23.3 shows the timing for a UART0 transaction with parity
enabled (PE0 = 1). Figure 23.4 is an example of a UART0 transaction when the extra bit is enabled
(XBE0 = 1). Note that the extra bit feature is not available when parity is enabled, and the second stop bit
is only an option for data lengths of 6, 7, or 8 bits.
SPACE
SPACE
MARK
MARK
BIT TIMES
BIT TIMES
SPACE
MARK
BIT TIMES
START
START
BIT
BIT
START
Figure 23.2. UART0 Timing Without Parity or Extra Bit
BIT
D
D
Figure 23.4. UART0 Timing With Extra Bit
0
0
Figure 23.3. UART0 Timing With Parity
D
0
D
D
1
1
N bits; N = 5, 6, 7, or 8
N bits; N = 5, 6, 7, or 8
D
1
N bits; N = 5, 6, 7, or 8
Rev. 1.1
D
D
N-2
N-2
D
N-2
C8051F55x/56x/57x
D
D
N-1
N-1
D
N-1
PARITY
EXTRA
STOP
BIT 1
STOP
STOP
BIT 1
BIT 1
Optional
(6,7,8 bit
STOP
BIT 2
Data)
Optional
Optional
(6,7,8 bit
(6,7,8 bit
STOP
STOP
BIT 2
Data)
BIT 2
Data)
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