C8051F555-IMR Silicon Labs, C8051F555-IMR Datasheet - Page 147

• Manufacturer Part Number: C8051F555-IMR
• Description: 8-bit Microcontrollers - MCU 50 MIPS 16 kB 2 kB CAN2.0 SPI
• Manufacturer: Silicon Labs

Specifications of C8051F555-IMR

• Rohs: yes
• Core: 8051
• Processor Series: C8051
• Data Bus Width: 8 bit

17.4. Multiplexed Mode
The External Memory Interface operates only in a Multiplexed mode. In Multiplexed mode, the Data Bus
and the lower 8-bits of the Address Bus share the same Port pins: AD[7:0]. In this mode, an external latch
(74HC373 or equivalent logic gate) is used to hold the lower 8-bits of the RAM address. The external latch
is controlled by the ALE (Address Latch Enable) signal, which is driven by the External Memory Interface
logic. An example of a Multiplexed Configuration is shown in Figure 17.1.
In Multiplexed mode, the external MOVX operation can be broken into two phases delineated by the state
of the ALE signal. During the first phase, ALE is high and the lower 8-bits of the Address Bus are pre-
sented to AD[7:0]. During this phase, the address latch is configured such that the Q outputs reflect the
states of the ‘D’ inputs. When ALE falls, signaling the beginning of the second phase, the address latch
outputs remain fixed and are no longer dependent on the latch inputs. Later in the second phase, the Data
Bus controls the state of the AD[7:0] port at the time RD or WR is asserted.
See Section “17.6.1. Multiplexed Mode” on page 151 for more information.
E
M
I
F
AD[7:0]
A[15:8]
/WR
ALE
/RD
Figure 17.1. Multiplexed Configuration Example
ADDRESS/DATA BUS
ADDRESS BUS
Rev. 1.1
V
DD
8
(Optional)
74HC373
G
D
C8051F55x/56x/57x
Q
A[15:8]
A[7:0]
I/O[7:0]
CE
WE
OE
64 K X 8
SRAM
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