MAX9272GTM+T Maxim Integrated, MAX9272GTM+T Datasheet
MAX9272GTM+T
Specifications of MAX9272GTM+T
Related parts for MAX9272GTM+T
MAX9272GTM+T Summary of contents
Page 1
GMSL Deserializer for Coax or STP Cable General Description The MAX9272 compact deserializer is designed to interface with a GMSL serializer over 50I coax or 100I shielded twisted-pair (STP) cable. The device pairs with the MAX9271 or MAX9273 serializers. ...
Page 2
... START and STOP Conditions Bit Transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Acknowledge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Slave Address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Bus Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Format for Writing Format for Reading . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Communication with Remote-Side Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Address Translation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Control-Channel Broadcast Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 GPO /GPI Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 PRBS Test . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Maxim Integrated TABLE OF CONTENTS 2 C Devices with UART MAX9272 2 ...
Page 3
... Software Programming of the Device Addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 Three-Level Configuration Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 Configuration Blocking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 Compatibility with other GMSL Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 GPIOs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 Staggered Parallel Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 Local Control-Channel Enable (LCCEN Internal Input Pulldowns . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 Choosing I 2 C/UART Pullup Resistors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 AC-Coupling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 Selection of AC-Coupling Capacitors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 Power-Supply Circuits and Bypassing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 Maxim Integrated TABLE OF CONTENTS (continued) MAX9272 3 ...
Page 4
... Figure 17. GMSL UART Data Format for Base Mode Figure 18. SYNC Byte (0x79 Figure 19. ACK Byte (0xC3 Figure 20. Format Conversion Between GMSL UART and I Figure 21. Format Conversion Between GMSL UART and I Maxim Integrated TABLE OF CONTENTS (continued) LIST OF FIGURES 2 C with Register Address (I2CMETHOD = with Register Address (I2CMETHOD = 1) ...
Page 5
... Table 11. MAX9272 Feature Compatibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 Table 12. Staggered Output Delay Table 13. Double-Function Configuration Table 14. Typical Power-Supply Currents (Using Worst-Case Input Pattern Table 15. Suggested Connectors and Cables for GMSL Table 16. Register Table (see Table Maxim Integrated LIST OF FIGURES (continued) LIST OF TABLES Table 16 MAX9272 ...
Page 6
... Mid-Level Input Current Input Current SINGLE-ENDED OUTPUTS (DOUT_, PCLKOUT) High-Level Output Voltage Low-Level Output Voltage Maxim Integrated Junction Temperature .....................................................+150°C Operating Temperature Range ........................ -40°C to +105°C Storage Temperature Range ............................ -65°C to +150°C Lead Temperature (soldering, 10s) ................................+300°C Soldering Temperature (reflow) ......................................+260°C *EP is connected to PCB ground. ) ............25° ...
Page 7
... Voltage Differential Low Input Threshold (Peak) Voltage Input Common-Mode Voltage (( -))/ Differential Input Resistance (Internal) Maxim Integrated = 1.7V to 3.6V 100I Q1% (differential), EP connected to PCB ground AVDD DVDD SYMBOL CONDITIONS 0V, IOVDD O DCS = 0 V IOVDD DOUT_ ...
Page 8
... V AVDD DVDD IOVDD +105°C, unless otherwise noted. Typical values are at V PARAMETER PARALLEL CLOCK OUTPUT (PCLKOUT) Clock Frequency Clock Duty Cycle Clock Jitter Maxim Integrated = 1.7V to 3.6V 100I Q1% (differential), EP connected to PCB ground AVDD DVDD SYMBOL CONDITIONS Activity detector, medium threshold ...
Page 9
... IN Note 4: Specified pin to ground. Note 5: Specified pin to all supply/ground. Note 6: Guaranteed by design and not production tested. Note 7: Measured in serial link bit times. Bit time = 1/( Maxim Integrated = 1.7V to 3.6V 100I Q1% (differential), EP connected to PCB ground ...
Page 10
... PCLKOUT FREQUENCY (MHz) OUTPUT POWER SPECTRUM vs. PCLKOUT FREQUENCY (VARIOUS SPREAD) 0 -10 0% SPREAD -20 -30 -40 -60 -60 -70 1% SPREAD -80 2% SPREAD -90 18.5 19.0 19.5 20.0 PCLKOUT FREQUENCY (MHz) Maxim Integrated Typical Operating Characteristics = +25°C, unless otherwise noted 20MHz PCLKOUT 4% SPREAD 20.5 21.0 21.5 MAX9272 SUPPLY CURRENT vs ...
Page 11
... PE, EQ OFF NO PE, 10.7dB PE, EQ OFF BER CAN BE AS LOW AS 10 CABLE LENGTHS LESS THAN 10m STP CABLE LENGTH (m) Maxim Integrated Typical Operating Characteristics (continued) = +25°C, unless otherwise noted.) A MAX9272 toc07 1.5Gbps 10 ) -12 FOR 15 20 MAXIMUM PCLKOUT FREQUENCY vs ...
Page 12
... Set DBL = low to use single-input mode. 3 CX/TP Coax/Twisted-Pair Three-Level Configuration Input (Table Select. Control-channel interface protocol select input with internal pulldown to EP. 4 I2CSEL Set I2CSEL = high to select I Maxim Integrated MAX9272 43 44 ...
Page 13
... Decoded horizontal sync for upper half of single-output when VS/HS encoding is enabled (Table 2). Parallel Data/Vertical Sync 0 Output. Defaults to parallel data input on power-up. 18 DOUT25/VS0 Parallel data output when VS/HS encoding is disabled. Decoded vertical sync for lower half of single-output when VS/HS encoding is enabled (Table 2). Maxim Integrated FUNCTION master/slave. RX/SDA has an open-drain driver and requires a pullup resistor master/slave ...
Page 14
... Exposed Pad internally connected to device ground. MUST connect EP to the PCB ground — EP plane through an array of vias for proper thermal and electrical performance. PCLKOUT DOUT [23:0] DOUT24/HS0 DOUT25 / VS0 DOUT26/HS1 DOUT27/ VS1 GPIO0/DBL GPIO1/BWS GPIO GPI Maxim Integrated FUNCTION SSPLL CLKDIV CDRPLL SERIAL PARALLEL FIFO SCRAMBLE/ 1x[27:0] CRC/ OR HAMMING/ 2x[10:0] 8b/10b ...
Page 15
... GMSL Deserializer for Coax or STP Cable V CMR V ROH 0 ROH 0 ROH (IN+) - (IN-) Figure 1. Reverse Control-Channel Output Parameters Maxim Integrated REVERSE CONTROL-CHANNEL TRANSMITTER IN+ IN MAX9272 IN CMR IN IN- IN+ 0 ROL 0 ROL ROL 15 ...
Page 16
... V IN- _ Figure 2. Test Circuit for Differential Input Measurement PCLKOUT Figure 4. Parallel Clock Output High and Low Times START CONDITION PROTOCOL (S) t SU;STA SCL t BUF SDA t HD;STA 2 Figure Timing Parameters Maxim Integrated IN+ V ID(P) IN ID(P) = IN+ IN )/2 CMR = ...
Page 17
... Figure 6. Output Rise-and-Fall Times SERIAL-WORD LENGTH SERIAL WORD N IN+/- FIRST BIT DOUT_ PARALLEL WORD N-2 PCLKOUT NOTE: PCLKOUT PROGRAMMED FOR RISING LATCHING EDGE. Figure 7. Deserializer Delay Figure 8. GPI-to-GPO Delay Maxim Integrated C L SINGLE-ENDED OUTPUT LOAD 0 I0VDD 0 I0VDD t R SERIAL WORD N+1 ...
Page 18
... UART protocol allows full-duplex communication, while allows half-duplex communication. Spread spectrum is available to reduce EMI on the paral- lel output. The serial input complies with ISO 10605 and IEC 61000-4-2 ESD protection standards. Maxim Integrated IN+/- PWDN V OH LOCK Figure 10. Power-Up Delay Registers set the operating conditions of the deserializer and are programmed using the control channel in base mode ...
Page 19
... FIRST WORD (FROM LATCH B) NOTE: DIAGRAM SHOWS POSSIBLE LOCATIONS FOR TRANSITIONS ON VS_ /HS_. VS_ /HS_ HAVE MINIMUM LENGTH REQUIREMENTS. NOTE: HS_, VS_ ACTIVE ONLY WHEN HVEN = 1. Figure 12. Single-Output Waveform (Serializer Using Double Input) Maxim Integrated SECOND WORD VS (FROM SECOND WORD) VS (FROM THIRD WORD) ...
Page 20
... DBL = 1) NOTE: DIAGRAM SHOWS POSSIBLE LOCATIONS FOR TRANSITIONS ON VS0 /HS0. VS0 /HS0 HAVE MINIMUM LENGTH REQUIREMENTS. NOTE: HS0, VS0 ACTIVE ONLY WHEN HVEN = 1. Figure 14. Double-Output Waveform (Serializer Using Double Input) Maxim Integrated DOUTB FIRST WORD FIRST WORD DOUTB FIRST WORD DOUTB FIRST WORD ...
Page 21
... HVTRACK = HS/VS tracking setting determined by the state of LCCEN and MS/HVEN at startup HVEN = HS/VS tracking encoding setting determined by the state of LCCEN and MS/HVEN at startup EDC = 00 or 10, error-detection/correction setting determined by the state of LCCEN and RX/SDA/EDC at startup Maxim Integrated Table 16) POWER-UP DEFAULT SETTINGS (MSB FIRST) 2 ...
Page 22
... RESERVED = 00100XXX 0x16 0x30 RESERVED = 00110000 0x17 0x54 RESERVED = 01010100 0x18 0x30 RESERVED = 00110000 Maxim Integrated Table 16) (continued) POWER-UP DEFAULT SETTINGS (MSB FIRST address translator source A is 0x00 2 C address translator destination A is 0x00 2 C address translator source B is 0x00 ...
Page 23
... DOUTA output on the first cycle of PCLKOUT and DOUTB output on the second cycle of PCLKOUT. Maxim Integrated Table POWER-UP DEFAULT SETTINGS HVEN DOUTA 0 0:21 1 0:17, 20:21, HS 0:10 1 0:10, HS 0:21 1 0:17, 20:21, HS 0:14 1 0:14, HS, VS ...
Page 24
... VIDEO AND ERROR CORRECTION DATA NOTE: SERIAL DATA SHOWN BEFORE SCRAMBLING AND 8b/10b ENCODING Figure 15. Serial-Data Format Maxim Integrated opposite direction of the video stream. The reverse control channel and forward video data coexist on the same serial cable, forming a bidirectional link. The reverse control channel operates independently from the forward control channel ...
Page 25
... DEV ADDR + R/W SYNC DEV ADDR + R/W Figure 16. GMSL UART Protocol for Base Mode Maxim Integrated The deserializer uses differential line coding to send signals over the reverse channel to the serializer. The bit rate of the control channel is 9.6kbps to 1Mbps in both directions. The serializer/deserializer automatically detect the control-channel bit rate in base mode ...
Page 26
... UART interface need to handle at least one PCLKOUT period Q 10ns of jitter due to the asynchronous sampling of the UART signal by PCLKOUT. Set MS/HVEN = high to put the control channel into bypass mode. For applications with the FC Maxim Integrated 1 UART FRAME ...
Page 27
... SYNC FRAME DEVICE SERIALIZER/DESERIALIZER PERIPHERAL 2 UART-TO-I C CONVERSION OF READ PACKET (I2CMETHOD = 1) SERIALIZER/DESERIALIZER SYNC FRAME DEVICE SERIALIZER/DESERIALIZER PERIPHERAL : MASTER TO SLAVE Figure 21. Format Conversion Between GMSL UART and I Maxim Integrated 11 11 REGISTER ADDRESS NUMBER OF BYTES DEV REG ADDR A ...
Page 28
... SDA BY RECEIVER S Figure 24. Acknowledge Maxim Integrated The acknowledge bit is a clocked 9th bit that the recipient uses to handshake receipt of each byte of data 24). Thus, each byte transferred effectively requires 9 bits. The master generates the 9th clock pulse, and the recipi- ent pulls down SDA during the acknowledge clock pulse. ...
Page 29
... REGISTER 0x00 WRITE DATA Figure 27. Format for Write to Multiple Registers Maxim Integrated Slave Address beyond storing the register address bytes received after the register address are data bytes. The first data byte goes into the register selected by the register address, and subsequent data bytes go into ...
Page 30
... Use address translation to assign unique device addresses to peripherals with limited addresses. Source addresses (address to translate from) are stored in registers 0x09 and 0x0B. Destination addresses (address to translate to) are stored in registers 0x0A and 0x0C. Maxim Integrated 0 = WRITE ADDRESS = 0x80 ...
Page 31
... Maxim Integrated PRBS Test spectrum modulation frequency within 20kHz to 40kHz. Additionally, manual configuration of the sawtooth divider (SDIV: 0x03, D[5:0]) allows the user to set a modulation frequency according to the PCLKOUT frequency. When ranges are manually selected, program the SDIV value for a fixed modulation frequency around 20kHz ...
Page 32
... Burst errors consecutive bits on the serial link are corrected and burst errors con- secutive bits are detected. Maxim Integrated Hamming code adds overhead similar to CRC. See for details regarding the available input word size. HS/VS encoding by a GMSL serializer allows horizontal and vertical synchronization signals to be transmit- ted while conserving pixel data bandwidth ...
Page 33
... SLEEP = 1. To wake up from the local side, send an arbitrary control- channel command to the deserializer, wait 5ms for the chip to power up, and then write 0 to the SLEEP register bit to make the wake-up permanent. To wake up from the Maxim Integrated MAX9272 GMSL IN+ SERIALIZER ...
Page 34
... SEREN = 1 and gets an 7 acknowledge. Waits for link to be established (~3ms). Maxim Integrated image-sensing applications. The control channel is avail- able after the video link or the configuration link is estab- lished. If the deserializer powers up after the serializer, the control channel becomes unavailable until 2ms after power-up ...
Page 35
... GPI CHANGES FROM LOW TO HIGH OR SEND GPI TO HIGH TO LOW GMSL SERIALIZER Figure 31. State Diagram, Remote Microcontroller Application Maxim Integrated SERIALIZER Sets all configuration inputs. If any configuration inputs are available on one end of the link but not on the other, always connects that configuration input low. ...
Page 36
... Contention occurs if both FCs attempt to use the control channel at the same time the user to prevent this contention by implementing a higher-level protocol. Maxim Integrated In addition, the control channel does not provide arbitra- tion between I acknowledge frame is not generated when communica- Error Checking tion fails due to contention ...
Page 37
... Double output Coax encoding Maxim Integrated level, a pulldown resistor to GND to set a low level, or IOVDD/2 or open to set a midlevel. For digital control, use three-state logic to drive the three-level logic input. The deserializer can block changes to registers. Set CFGBLOCK to make all registers read only. Once set, the registers remain blocked until the supplies are removed or until PWDN is low ...
Page 38
... I specifies 300ns rise times (30% to 70%) for fast mode, which is defined for data rates up to 400kbps (see the I specifications in the AC Electrical Characteristics table for details). To meet the fast-mode rise-time requirement, Maxim Integrated GPIO1/BWS MS/HVEN FUNCTION FUNCTION MS input ...
Page 39
... PCLK AVDD (MHz) (mA) 25 25.1 50 33.3 Maxim Integrated ), and The trace dimensions depend on the type of trace used TD (microstrip or stripline). Note that two 50I PCB traces do not have 100I differential impedance when brought TD close together—the impedance goes down when the traces are brought closer. Use a 50I trace for the single- ended output when driving coax ...
Page 40
... SS D[5:4] — 0x02 D[3:2] PRNG D[1:0] SRNG D[7:6] AUTOFM 0x03 D5 — D[4:0] SDIV Maxim Integrated D DEVICE UNDER TEST Figure 34. ISO 10605 Contact Discharge ESD Test Circuit Table 1) VALUE XXXXXXX Serializer device address. 0 Reserved. Deserializer device address. Default address is XXXXXXX determined by the state of the CX/TP input (Table 8). ...
Page 41
... D5 PRBSEN D4 SLEEP 0x04 D[3:2] INTTYPE D1 REVCCEN D0 FWDCCEN D7 I2CMETHOD D6 DCS D5 HVTRMODE D4 ENEQ 0x05 D[3:0] EQTUNE Maxim Integrated Table 1) (continued) VALUE FUNCTION 0 LOCK output is low. 1 LOCK output is high. 0 Enable outputs. 1 Disable outputs. 0 Disable PRBS test. 1 Enable PRBS test. 0 Normal mode. 1 Activate sleep mode. 00 Local control channel uses I 01 Local control channel uses UART when I2CSEL = 0 ...
Page 42
... D7 DBL D6 DRS D5 BWS D4 ES 0x07 D3 HVTRACK D2 HVEN D[1:0] EDC Maxim Integrated Table 1) (continued) VALUE 00000010 Reserved. Single-input mode. Power-up default when LCCEN = 0 high or GPIO0/DBL = low. Double-input mode. Power-up default when LCCEN = 1 low and GPIO0/DBL = high. 0 High data-rate mode. 1 Low data-rate mode. ...
Page 43
... D0 — D[7:1] I2CSRCB 0x0B D0 — D[7:1] I2CDSTB 0X0C D0 — Maxim Integrated Table 1) (continued) VALUE DOUT0 inversion. Invert VS when HVEN = 1. Invert DOUT0 when HVEN = not use if DBL = 0 in the deserializer and DBL = 1 in the serializer DOUT1 inversion. Invert HS when HVEN = 1. Invert DOUT1 when 1 HVEN = 0 ...
Page 44
... D2 GPIO1IN D1 GPIO0OUT D0 GPIO0IN 0x0F D[7:0] DETTHR 0x10 D[7:0] DETERR 0x11 D[7:0] CORRTHR 0x12 D[7:0] CORRERR Maxim Integrated Table 1) (continued) VALUE Acknowledge not generated when forward channel is not 0 available C-to slave generates local acknowledge when 1 forward channel is not available. 00 352ns/117ns setup/hold time. 01 469ns/234ns setup/hold time ...
Page 45
... CXSEL 0x1D D5 I2CSEL D4 LCCEN D[3:0] — 0x1E D[7:0] ID D[7:5] — 0x1F D4 CAPS D[3:0] REVISION X = Don’t care. Maxim Integrated Table 1) (continued) VALUE XXXXXXXX PRBS error counter. 0 PRBS test not completed. 1 PRBS test completed with success. 000000 Reserved. 00100XXX Reserved. 00110000 Reserved. 01010100 Reserved. 00110000 Reserved. ...
Page 46
... Exposed pad. **Future product—contact factory for availability. Chip Information PROCESS: CMOS Maxim Integrated CAMERA APPLICATION MAX9271 OUT+ OUT- For the latest package outline information and land patterns (foot- PIN-PACKAGE prints www.maximintegrated.com/packages. Note that a 48 TQFN-EP* “ ...
Page 47
... Maxim Integrated cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim Integrated product. No circuit patent licenses are implied. Maxim Integrated reserves the right to change the circuitry and specifications without notice at any time. The parametric values (min and max limits) shown in the Electrical Characteristics table are guaranteed ...