MAX9257AGCM/V+T Maxim Integrated, MAX9257AGCM/V+T Datasheet - Page 42

• Manufacturer Part Number: MAX9257AGCM/V+T
• Description: Serializers & Deserializers - Serdes Prog Serializer / Deserializer
• Manufacturer: Maxim Integrated
• Type: Serializerr

Specifications of MAX9257AGCM/V+T

• Rohs: yes
• Data Rate: 840 Mbit/s
• Input Type: LVCMOS
• Output Type: LVDS
• Number Of Inputs: 18
• Number Of Outputs: 1
• Operating Supply Voltage: 1.7 V to 3.6 V
• Operating Temperature Range: - 40 C to + 105 C
• Package / Case: LQFP-48
• Maximum Operating Temperature: + 105 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Supply Voltage - Max: 3.6 V
• Supply Voltage - Min: 1.71 V, 3 V

Voltage droop and the digital sum variaton (DSV) of
trans mitted symbols cause signal transitions to start
from dif ferent voltage levels. Because the transition time
is finite, starting the signal transition from different volt-
age levels causes timing jitter. The time constant for an
AC-coupled link needs to be chosen to reduce droop
and jitter to an acceptable level. The RC network for an
AC-coupled link consists of the LVDS receiver termina-
tion resistor (R
(R
RC time constant for four equal-value series capacitors is
(C x (R
the transmission line impedance (usually 100I). This
leaves the capacitor selection to change the system time
constant. In the fol lowing example, the capacitor value
for a droop of 2% is calculated:
where:
C = AC-coupling capacitor (F)
t
DSV = digital sum variation (integer)
ln = natural log
D = droop (% of signal amplitude)
R
R
The bit time (t
of the pixel clock divided by the total number of bits. The
maximum DSV for the MAX9257A encoding equals to the
total number of bits transmitted in one pixel clock cycle.
This means that t
The capacitor for 2% maximum droop at 16MHz paral lel
rate clock is:
Total number of bits is = 10 (data) + 2 (HSYNC and
VSYNC) + 2 (encoding) + 2 (parity) = 16
C ≥ 0.062FF
B
TD
TR
TD
= bit time(s)
= receiver termination resistor (I)
= driver termination resistor (I)
), and the series AC-coupling capacitors (C). The
TD
Optimally Choosing AC-Coupling Capacitors
+ R
TR
C -
B
TR
C
C -
) is the serial-clock period or the period
=
))/4. RTD and RTR are required to match
B
= −
), the LVDS driver termination resistor
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=
ln(1 - .02) (100
x DSV = t
Fully Programmable Serializer/Deserializer
ln(1 - D) (R
ln(1 - D) (R
4 3.91ns 16
4 t
×
4 t
×
×
×
×
×
B
T
B
.
×
×
TR
TR
DSV
DSV
×
Ω +
+
+
R
R
100 )
TD
TD
)
)
Ω
with UART/I
Jitter due to droop is proportional to the droop and tran-
sition time:
t
where:
t
t
D = droop (% of signal amplitude)
Jitter due to 2% droop and assumed 1ns transition time is:
t
t
The transition time in a real system depends on the fre-
quency response of the cable driven by the serializer.
The capacitor value decreases for a higher frequency
parallel clock and for higher levels of droop and jitter.
Use high-frequency, surface-mount ceramic capacitors.
All single-ended inputs and outputs on the MAX9257A
are powered from V
MAX9258A are powered from V
can be connected to a +1.71V to +3.6V sup ply. The input
levels or output levels scale with these supply rails.
Separate the LVCMOS/LVTTL signals and LVDS signals
to prevent crosstalk. A four-layer PCB with separate
lay ers for power, ground, LVDS, and digital signals is
rec ommended. Layout PCB traces for 100I differential
characteristic impedance. The trace dimensions depend
on the type of trace used (microstrip or stripline). Note
that two 50I PCB traces do not have 100I differential
impedance when brought close together—the imped-
ance goes down when the traces are brought closer.
Route the PCB traces for an LVDS channel (there are
two conductors per LVDS channel) in parallel to main tain
the differential characteristic impedance. Place the 100I
(typ) termination resistor at both ends of the LVDS driver
and receiver. Avoid vias. If vias must be used, use only
one pair per LVDS channel and place the via for each
line at the same point along the length of the PCB traces.
This way, any reflections occur at the same time. Do not
make vias into test points for ATE. Make the PCB traces
that make up a differential pair the same length to avoid
skew within the differen tial pair.
J
J
TT
J
J
= t
= jitter(s)
= 1ns x 0.02
= 20ps
= transition time(s) (0 to 100%)
TT
MAX9257A/MAX9258A
x D
Power-Supply Circuits and Bypassing
2
C Control Channel
CCIO
. All single-ended outputs on the
CCOUT
. V
CCIO
Board Layout
and V
CCOUT