PCA9535ECDWR2G ON Semiconductor, PCA9535ECDWR2G Datasheet - Page 10

• Manufacturer Part Number: PCA9535ECDWR2G
• Description: Interface - I/O Expanders 16-BIT I/O EXPANDER
• Manufacturer: ON Semiconductor

Specifications of PCA9535ECDWR2G

• Rohs: yes
• Logic Family: PCA9535
• Number Of I/os: 16
• Maximum Operating Frequency: 400 KHz
• Operating Supply Voltage: 1.65 V to 5.5 V
• Operating Temperature Range: - 55 C to + 125 C
• Mounting Style: SMD/SMT
• Package / Case: SOIC-24
• Interface Type: I2C, SMBus
• Interrupt Output: Yes
• Operating Current: 1.65 V to 5.5 V
• Output Current: 50 mA
• Power Dissipation: 600 mW
• Product Type: I/O Expanders

Registers 4 and 5: Polarity Inversion Registers
port registers to be inverted. The input port data polarity will
Registers 6 and 7: Configuration Registers
configuration registers. When a bit in the configuration
registers is set (written with ‘1’), the bit’s corresponding port
Power−on Reset
(POR) holds the PCA9535E/PCA9535EC in a reset
condition while V
V
PCA9535E/PCA9535EC registers and SMBus state
machine will initialize to their default states. The reset is
typically completed by the POR and the part enabled by the
time the power supply is above V
a power reset cycle, it is necessary to lower the power supply
below 0.2 V, and then restored to the operating voltage.
I/O Port (See Figure 2)
PCA9535E, FETs Q1 and Q2 are off, creating a
Table 12. POLARITY INVERSION PORT 0 REGISTER
Symbol
Default
Table 13. POLARITY INVERSION PORT 1 REGISTER
Symbol
Default
Table 14. CONFIGURATION PORT 0 REGISTER
Symbol
Default
Table 15. CONFIGURATION PORT 1 REGISTER
Symbol
Default
POR
These registers allow the polarity of the data in the input
The I/O pin directions are configured through the
Upon application of power, an internal Power−On Reset
When an I/O pin is configured as an input on the
,
Bit
Bit
Bit
Bit
the
reset
DD
N0.7
N1.7
C0.7
C1.7
is ramping up. When V
condition
7
0
7
0
7
1
7
1
POR
N0.6
N1.6
C0.6
C1.6
is
6
0
6
0
6
1
6
1
. However, when doing
released
DD
has reached
N0.5
N1.5
C0.5
C1.5
5
0
5
0
5
1
5
1
and the
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10
N0.4
N1.4
C0.4
C1.4
4
0
4
0
4
1
4
1
be inverted when its corresponding bit in these registers is
set (written with ‘1’), and retained when the bit is cleared
(written with a ‘0’).
pin is enabled as an input with the output driver in
high−impedance. When a bit is cleared (written with ‘0’),
the corresponding port pin is enabled as an output. At reset,
the device’s ports are inputs.
high−impedance input. The input voltage may be raised
above V
PCA9535EC, FET Q1 has been removed and the
open−drain FET Q2 will function the same as PCA9535E.
PCA9535E, then either Q1 or Q2 is enabled, depending on
the state of the output port register. With the PCA9535EC,
an external pullup is required to pull the I/O pin HIGH when
its corresponding output port register bit is a 1. Care should
be exercised if an external voltage is applied to an I/O
configured as an output because of the low−impedance path
that exists between the pin and either V
When the I/O pin is configured as an output on the
DD
N0.3
N1.3
C0.3
C1.3
3
0
3
0
3
1
3
1
to a maximum of 5.5 V. In the case of
N0.2
N1.2
C0.2
C1.2
2
0
2
0
2
1
2
1
N0.1
N1.1
C0.1
C1.1
1
0
1
0
1
1
1
1
DD
or V
SS
.
N0.0
N1.0
C0.0
C1.0
0
0
0
0
0
1
0
1