PCA9538APWJ NXP Semiconductors, PCA9538APWJ Datasheet - Page 6

• Manufacturer Part Number: PCA9538APWJ
• Description: Interface - I/O Expanders 8bit I2C IO Port
• Manufacturer: NXP Semiconductors

Specifications of PCA9538APWJ

• Rohs: yes
• Maximum Operating Frequency: 100 kHz
• Operating Supply Voltage: 1.65 V to 5.5 V
• Operating Temperature Range: - 40 C to + 85 C
• Mounting Style: SMD/SMT
• Package / Case: TSSOP-16
• Operating Current: 160 mA
• Output Current: 25 mA
• Power Dissipation: 200 mW
• Product Type: I/O Expanders

NXP Semiconductors
PCA9538A
Product data sheet
6.4.1 Input port register (00h)
6.4.2 Output port register (01h)
6.4.3 Polarity inversion register (02h)
6.3 Interface definition
6.4 Register descriptions
Table 5.
The Input port register (register 0) reflects the incoming logic levels of the pins, regardless
of whether the pin is defined as an input or an output by the Configuration register. The
Input port register is read only; writes to this register have no effect. The default value ‘X’
is determined by the externally applied logic level. An Input port register read operation is
performed as described in
Table 6.
The Output port register (register 1) shows the outgoing logic levels of the pins defined as
outputs by the Configuration register. Bit values in these registers have no effect on pins
defined as inputs. In turn, reads from this register reflect the value that was written to this
register, not the actual pin value.
Table 7.
The Polarity inversion register (register 2) allows polarity inversion of pins defined as
inputs by the Configuration register. If a bit in this register is set (written with ‘1’), the
corresponding port pin’s polarity is inverted. If a bit in this register is cleared (written with a
‘0’), the corresponding port pin’s original polarity is retained.
Table 8.
Byte
I
I/O data bus
Bit
Symbol
Default
Bit
Symbol
Default
Bit
Symbol
Default
2
C-bus slave address
Interface definition
Input port register (address 00h)
Output port register (address 01h)
Polarity inversion register (address 02h)
O7
N7
I7
X
7
7
1
7
0
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 28 September 2012
O6
N6
7 (MSB)
I6
X
6
6
1
6
0
P7
H
Section 7.2 “Read
Low-voltage 8-bit I
O5
N5
I5
X
5
5
1
5
0
P6
H
6
P5
O4
N4
H
5
I4
X
4
4
1
4
0
commands”.
2
C-bus I/O port with interrupt and reset
P4
4
L
O3
N3
I3
X
3
3
1
3
0
Bit
P3
3
L
O2
N2
I2
X
2
2
1
2
0
A1
P2
PCA9538A
2
© NXP B.V. 2012. All rights reserved.
O1
N1
I1
X
1
1
1
1
0
A0
P1
1
0 (LSB)
R/W
P0
O0
N0
I0
X
0
0
1
0
0
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