MC100ELT23DTG ON Semiconductor, MC100ELT23DTG Datasheet

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MC100ELT23DTG

Manufacturer Part Number
MC100ELT23DTG
Description
IC XLATOR DL PECL-TTL DFF 8TSSOP
Manufacturer
ON Semiconductor
Series
100ELTr
Datasheet

Specifications of MC100ELT23DTG

Logic Function
Translator
Number Of Bits
2
Input Type
PECL
Output Type
TTL
Number Of Channels
2
Number Of Outputs/channel
1
Differential - Input:output
Yes/No
Propagation Delay (max)
5.5ns
Voltage - Supply
4.75 V ~ 5.25 V
Operating Temperature
-40°C ~ 85°C
Package / Case
8-TSSOP
Supply Voltage
4.75 V ~ 5.25 V
Logic Type
Translator
Logic Family
ECL
Translation
PECL to TTL
Propagation Delay Time
5.5 ns
Supply Voltage (max)
5.25 V
Supply Voltage (min)
4.75 V
Maximum Operating Temperature
+ 85 C
Minimum Operating Temperature
- 40 C
Mounting Style
SMD/SMT
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Data Rate
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
MC100ELT23DTGOS
MC100ELT23
5 V Dual Differential PECL
to TTL Translator
Description
Because PECL (Positive ECL) levels are used, only +5 V and ground
are required. The small outline 8-lead package and the dual gate
design of the ELT23 makes it ideal for applications which require the
translation of a clock and a data signal.
accept any standard differential PECL input referenced from a V
5.0 V.
Features
© Semiconductor Components Industries, LLC, 2009
March, 2009 − Rev. 16
The MC100ELT23 is a dual differential PECL to TTL translator.
The PECL inputs are differential; therefore, the MC100ELT23 can
3.5 ns Typical Propagation Delay
24 mA TTL Outputs
Flow Through Pinouts
The 100 Series Contains Temperature Compensation
Operating Range V
Internal Input 50 KW Pulldown Resistors
Pb−Free Packages are Available
CC
= 4.75 V to 5.25 V with GND = 0 V
1
CC
of
See detailed ordering and shipping information in the package
dimensions section on page 4 of this data sheet.
*For additional marking information, refer to
(Note: Microdot may be in either location)
Application Note AND8002/D.
8
8
ORDERING INFORMATION
1
MARKING DIAGRAMS*
1
A
L
Y
W
M
G
http://onsemi.com
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Date Code
= Pb−Free Package
CASE 506AA
CASE 948R
MN SUFFIX
DT SUFFIX
CASE 751
D SUFFIX
TSSOP−8
SOIC−8
DFN8
Publication Order Number:
8
1
MC100ELT23/D
8
1
KLT23
ALYW
ALYWG
1
KT23
G
G
4

Related parts for MC100ELT23DTG

MC100ELT23DTG Summary of contents

Page 1

MC100ELT23 5 V Dual Differential PECL to TTL Translator Description The MC100ELT23 is a dual differential PECL to TTL translator. Because PECL (Positive ECL) levels are used, only +5 V and ground are required. The small outline 8-lead package and the ...

Page 2

PECL TTL Figure 1. 8−Lead Pinout (Top View) and Logic Diagram Table 2. ATTRIBUTES Internal Input Pulldown Resistor Internal Input Pullup Resistor ESD Protection Moisture Sensitivity, Indefinite Time Out of Drypack (Note ...

Page 3

Table 4. PECL INPUT DC CHARACTERISTICS Symbol Characteristic V Input HIGH Voltage (Single−Ended) (Note Input LOW Voltage (Single−Ended Input HIGH Voltage Common Mode Range IHCMR (Differential) (Note 5) I Input HIGH Current IH I Input ...

Page 4

... Figure 2. TTL Output Loading Used for Device Evaluation ORDERING INFORMATION Device MC100ELT23D MC100ELT23DG MC100ELT23DR2 MC100ELT23DR2G MC100ELT23DT MC100ELT23DTG MC100ELT23DTR2 MC100ELT23DTR2G MC100ELT23MNR4 MC100ELT23MNR4G †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. APPLICATION ...

Page 5

Resource Reference of Application Notes AN1405/D − ECL Clock Distribution Techniques AN1406/D − Designing with PECL (ECL at +5.0 V) AN1503/D − ECLinPSt I/O SPiCE Modeling Kit AN1504/D − Metastability and the ECLinPS Family AN1568/D − Interfacing Between LVDS and ...

Page 6

... G C SEATING PLANE −Z− 0.25 (0.010 *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. PACKAGE DIMENSIONS SOIC−8 NB CASE 751−07 ISSUE 0.10 (0.004 SOLDERING FOOTPRINT* 1 ...

Page 7

K 8x REF 0.10 (0.004) 0.15 (0.006 L −U− PIN 1 IDENT 0.15 (0.006 −V− C 0.10 (0.004) D −T− G SEATING PLANE PACKAGE DIMENSIONS TSSOP−8 ...

Page 8

... Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. PUBLICATION ORDERING INFORMATION LITERATURE FULFILLMENT: Literature Distribution Center for ON Semiconductor P.O. Box 5163, Denver, Colorado 80217 USA Phone: 303−675−2175 or 800−344−3860 Toll Free USA/Canada Fax: 303− ...

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