MAX3394EEBL+T Maxim Integrated Products, MAX3394EEBL+T Datasheet - Page 8

• Manufacturer Part Number: MAX3394EEBL+T
• Description: IC LVL XLTR LV 6MBPS PP 9-UCSP
• Manufacturer: Maxim Integrated Products

Specifications of MAX3394EEBL+T

• Logic Function: Translator, Bidirectional, 3-State
• Number Of Bits: 2
• Input Type: Logic
• Output Type: Logic
• Data Rate: 6Mbps
• Number Of Channels: 2
• Number Of Outputs/channel: 1
• Differential - Input:output: No/No
• Propagation Delay (max): 50ns
• Voltage - Supply: 1.65 V ~ 5.5 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 9-UCSP®
• Supply Voltage: 1.65 V ~ 5.5 V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: MAX3394EEBL+T; MAX3394EEBL+TTR

The MAX3394E/MAX3395E/MAX3396E feature a tri-
state output mode, thermal-shutdown protection, and
±15kV Human Body Model (HBM) ESD protection on
the V
route signals externally.
The MAX3394E/MAX3395E/MAX3396E accept V
ages from +1.65V to +5.5V, and V
to V
voltage ASIC/PLDs and higher voltage systems. The
MAX3394E/MAX3395E/MAX3396E operate at a guaran-
±15kV ESD-Protected, High-Drive Current, Dual-/Quad-/
Octal-Level Translators with Speed-Up Circuitry
Figure 1. Push-Pull Driving I/O V
Figure 2. Open-Drain Driving I/O V
8
_______________________________________________________________________________________
CC
CC
, making them ideal for data transfer between low-
V
side for greater protection in applications that
GATE
I/O V
50Ω
I/O V
L_
V
V
L
L
L_
V
V
L
V
L
V
L
L
EN
L_
EN
MAX3394E
MAX3395E
MAX3396E
L_
MAX3394E
MAX3395E
MAX3396E
Test Circuit and Timing
Test Circuit and Timing
L
voltages from +1.2V
V
V
V
CC
V
CC
CC
CC
I/O V
I/O V
CC
CC_
CC_
volt-
V
V
C
CC
CC
C
IOVCC
IOVCC
teed data rate of 6Mbps with push-pull drivers and
1Mbps with open-drain drivers.
The MAX3394E/MAX3395E/MAX3396E utilize a trans-
mission gate architecture to provide bidirectional level
translation between I/O V
mission gate architecture is comprised of a pass-FET,
gate-control logic, and slew-rate enhancement circuit-
ry. When both I/O V
gate-control logic disables the pass-FET, providing
I/O V
CC
V
10%
GATE
50%
10%
50%
t
t
I/OVL-VCC
I/OVL-VCC
I/O V
t
L
RVCC
t
RVCC
L
90%
90%
_ and I/O V
50%
50%
L
I/O V
_ and I/O V
CC
t
I/OVL-VCC
t
I/OVL-VCC
CC
Level Translation
90%
50%
90%
50%
_ are logic high, the
t
FVCC
t
FVCC
50%
50%
CC
_. The trans-
10%
10%