NB7L216MNR2 ON Semiconductor, NB7L216MNR2 Datasheet - Page 9

no-image

NB7L216MNR2

Manufacturer Part Number
NB7L216MNR2
Description
IC RECEIVER/DRIVER DIFF 16-QFN
Manufacturer
ON Semiconductor
Datasheet

Specifications of NB7L216MNR2

Logic Type
Differential Receiver/Driver
Supply Voltage
2.375 V ~ 3.465 V
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
16-TFQFN Exposed Pad
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Number Of Bits
-
input signal (LVDS, PECL, or CML) are minimum input swing of 75 mV and the maximum input swing of 2500 mV. Within
these conditions, the input voltage can range from V
environment (Z = 50 W). For output termination and interface, refer to application note AND8020/D.
Table 7. INTERFACING OPTIONS
Recommended R
All NB7L216 inputs can accept PECL, CML, LVTTL, LVCMOS and LVDS signal levels. The limitations for differential
RSECL, PECL, NECL
Interfacing Options
LVTTL, LVCMOS
AC−COUPLED
5.0 V 290 W
3.3 V 150 W
2.5 V 80 W
V
CC
LVDS
CML
R
T
T
Values
Connect VTD and VTD to V
Connect VTD and VTD Together (See Figure 20)
Bias VTD and VTD Inputs within Common Mode Range (V
Standard ECL Termination Techniques (See Figure 13)
An External Voltage (V
V
V
THR
THR
PECL
Driver
V
V
is 1.5 V for LVTTL and V
Specification. (See Figure 21)
V
50 W
EE
V
CC
CC
EE
CML
Driver
*V
Bias
50 W
Figure 19. PECL to NB7L216 Interface
Figure 18. CML to NB7L216 Interface
must be within common mode range limits (V
R
V
APPLICATION INFORMATION
T
EE
THR
R
Q
Q
) should be Applied to the Unused Complementary Differential Input. Nominal
T
CC
http://onsemi.com
CC
(See Figure 18)
Z = 50 W
Z = 50 W
CC
/ 2 for LVCMOS Inputs. This Voltage must be within the
Z = 50 W
Z = 50 W
to 1.2 V. Examples interfaces are illustrated below in a 50 W
9
V
V
V
V
Connections
Bias
Bias
CC
CC
C
C
*
*
VTD
VTD
VTD
VTD
CMR
D
D
D
D
CMR
) (See Figure 19)
)
V
V
50 W
50 W
V
V
50 W
50 W
CC
CC
EE
EE
NB7L216
NB7L216

Related parts for NB7L216MNR2