ZADCS1022IS14T ZMDI, ZADCS1022IS14T Datasheet - Page 17

• Manufacturer Part Number: ZADCS1022IS14T
• Description: Analog to Digital Converters - ADC ADC
• Manufacturer: ZMDI

Specifications of ZADCS1022IS14T

• Product Category: Analog to Digital Converters - ADC
• Rohs: yes
• Number Of Channels: 2/1
• Architecture: SAR
• Conversion Rate: 250 KSPs
• Resolution: 10 bit
• Input Type: Single-Ended/Differential
• Snr: 61 dB
• Interface Type: Microwire, QSPI, SPI
• Operating Supply Voltage: 2.7 V to 5.25 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Package / Case: SSOP-14
• Maximum Power Dissipation: 250 mW
• Minimum Operating Temperature: - 25 C
• Number Of Converters: 1
• Voltage Reference: 2.5 V

In bipolar mode, IN
(IN
saturation. For instance, if IN
voltage of Vref/2, then IN
cover the entire code range. Lower or higher voltages of
IN
code value.
Figure 7 shows the input voltage ranges in bipolar mode
when IN
As explained before, converters out of the ZADCS10x2
family can also be used to convert fully differential input
signals that change around a common mode input
voltage.
The bipolar mode is best used for such purposes since
it allows the input signals to be positive or negative in
relation to each other.
The common mode level of a differential input signal is
calculated V
clipping or over steering of the converter, the common
mode level can change from ¼ V
this range the peak to peak amplitude of the differential
input signal can be ± V
The average input current on the analog inputs depends
on the conversion rate. The signal source must be
capable of charging the internal sampling capacitors
(typically 16pF on each input of the converter: IN
IN
accuracy. The equivalent input circuit in sampling mode
is shown in Figure 9.
The following equation provides a rough hand calculation for a source impedance R
out a DC input signal referenced to AGND with 8 bit accuracy in a given acquisition time
For example, if f
time is t
of the signal source R
If the output impedance of the source is higher
than the calculated maximum R
time must be extended by reducing f
ensure 8 bit accuracy. Another option is to add a
capacitor of > 20nF to the individual input.
Although this limits the bandwidth of the input
signal because an RC low pass filter is build
together with the source impedance, it may be
Data Sheet
October 12, 2011
R
R
+
–
ZADCS1082/1042/1022
10-Bit, 250ksps, ADC Family
S
S
–
) within the acquisition time t
keep the output code at the minimum or maximum


+Vref/2) keeping the converter out of code
7
7
758ns
t


–
ACQ
ACQ
C
is set to a constant DC voltage.
20pF
IN
= 758ns. Thus the output impedance
CM

= (V(IN

R
© 2011 Zentrum Mikroelektronik Dresden AG — Rev. 2.0
All rights reserved. The material contained herein may not be reproduced, adapted, merged, translated, stored, or used without
the prior written consent of the copyright owner. The information furnished in this publication is PRELIMINARY and subject to
changes without notice.
3
SW
SCLK
kΩ
+
S
can range from (IN
REF
= 3.3MHz, the acquisition
+

must be less than
)+ V(IN
2.41kΩ
+
/2.
can vary from 0V to V
–
is set to a constant DC
–
)) / 2. To avoid code
S
REF
the acquisition
ACQ
… ¾ V
to the required
–
SCLK
- Vref/2) to
REF
to
. Within
REF
+
and
Figure 9: Equivalent input circuit during sampling
to
COM
CH0
CH1
CH2
CH3
CH4
CH5
CH6
CH7
Multiplexer
Channel
Figure 8: Block diagram of input multiplexer
COM
CH0
CH1
CH2
CH3
CH4
CH5
CH6
CH7
See Table 5 & Table 6
for Coding Schemes
IN
IN
+
-
C
C
IN
IN
AGND
AGND
4pF
4pF
Shown configuration
C
C
A2 … A0 = 0x000
16pF
16pF
S
HOLD+
HOLD-
that is required to settle
SGL/DIF = HIGH
R
3kΩ
R
3kΩ
SW
SW
IN+
Converter
IN-
17 of 26
V
DC