MAX11629EEE+T Maxim Integrated, MAX11629EEE+T Datasheet - Page 10

• Manufacturer Part Number: MAX11629EEE+T
• Description: Analog to Digital Converters - ADC 12-Bit 8Ch 300ksps 3.6V Precision ADC
• Manufacturer: Maxim Integrated

Specifications of MAX11629EEE+T

• Rohs: yes
• Number Of Channels: 8
• Architecture: SAR
• Conversion Rate: 300 KSPs
• Resolution: 12 bit
• Input Type: Single-Ended
• Interface Type: 3-Wire (SPI, Microwire), QSPI
• Operating Supply Voltage: 2.7 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Maximum Power Dissipation: 667 mW
• Minimum Operating Temperature: - 40 C
• Number Of Converters: 1
• Voltage Reference: 2.048 V

12-Bit, 300ksps ADCs
with FIFO and Internal Reference
10
(4 CHANNELS)
MAX11626
MAX11627
______________________________________________________________________________________
5, 6, 7
1–4
10
11
12
13
14
15
16
—
—
—
—
8
9
(8 CHANNELS)
MAX11628
MAX11629
1–7
10
11
12
13
14
15
16
—
—
—
—
—
8
9
(16 CHANNELS)
MAX11632
MAX11633
1–15
16
17
18
19
20
21
22
23
24
—
—
—
—
—
CNVST/AIN15
CNVST/AIN7
AIN0–AIN14
AIN0–AIN6
AIN0–AIN3
CNVST
NAME
DOUT
SCLK
GND
EOC
N.C.
REF
V
DIN
CS
DD
No Connection. Not internally connected.
Analog Inputs
Analog Inputs
Analog Inputs
Active-Low Conversion Start Input/Analog Input 15.
See Table 3 for details on programming the setup
register.
Active-Low Conversion Start Input/Analog Input 7.
See Table 3 for details on programming the setup
register.
Active-Low Conversion Start Input. See Table 3 for
details on programming the setup register.
Reference Input. Bypass to GND with a 0.1µF
capacitor.
Ground
Power Input. Bypass to GND with a 0.1µF
capacitor.
Active-Low Chip-Select Input. When CS is low, the
serial interface is enabled. When CS is high, DOUT
is high impedance.
S er i al C l ock Inp ut. C l ocks d ata i n and out of the ser i al
i nter face. ( D uty cycl e m ust b e 40% to 60% .) S ee
Tab l e 3 for d etai l s on p r og r am m i ng the cl ock m od e.
Serial Data Input. DIN data is latched into the serial
interface on the rising edge of SCLK.
S er i al D ata Outp ut. D ata i s cl ocked out on the fal l i ng
ed g e of S C LK. H i g h i m p ed ance w hen CS i s
connected to V
End of Conversion Output. Data is valid after EOC
pulls low.
D D
.
FUNCTION
Pin Description