MAX9322ECY+TD Maxim Integrated, MAX9322ECY+TD Datasheet - Page 6

• Manufacturer Part Number: MAX9322ECY+TD
• Description: Communication ICs - Various
• Manufacturer: Maxim Integrated
• Type: Differential Divide-by-1/Divide-by-2 Clock Driverr

Specifications of MAX9322ECY+TD

• Package / Case: TQFP-52
• Supply Voltage - Max: +/- 3.8 V
• Supply Voltage - Min: +/- 2.375 V
• Supply Current: 66 mA
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Operating Supply Voltage: +/- 2.5 V, +/- 3.3 V
• Supply Type: Analog

DC-Coupled, UCSP 3.125Gbps Equalizer
______and Applications Information
The MAX3803 is an adaptive equalizer designed to
extend the reach of transmission lines in high-frequency
backplane and rack-to-rack interconnect applications.
The MAX3803 automatically adjusts to attenuation
caused by skin-effect and dielectric losses. Although
optimized for coded and scrambled data between
2.488Gbps and 3.125Gbps, the MAX3803 provides
effective compensation for rates between 1Gbps
and 3.2Gbps.
The MAX3803 consists of low common-mode input and
output buffers, an equalizer core, a DC-offset-correction
loop, and a limiting amplifier (Figure 2).
The MAX3803 permits DC-coupling to CML transmitters
and receivers that require termination voltages as low
as 1.1V and as high as V
to maintain compatible common-mode levels between
the data source and load. V
and can be used to bridge two common-mode require-
ments without the use of DC-blocking capacitors. See
Figure 3 and Figure 4 for the equivalent input and out-
put structures.
Figure 1. Backplane Interconnect
Figure 2. Functional Diagram
6
_______________Detailed Description
IN+
IN-
_______________________________________________________________________________________
≤40in EDGE-COUPLED TRANSMISSION LINE ON FR4 OR ≤10m 28AWG TWIN AX CABLE
SOURCE
SIGNAL
Low Common-Mode Input and Output
A
INPUT
CML
V
TI
2
CONNECTOR
CANCELLATION
EQUALIZER
LOOP
DC
2
CC
CONNECTOR
V
TI
CC
. Use the V
and V
AMPLIFER
LIMITING
TO
2
B
MAX3803
are independent
TI
MAX3803
IN
OUTPUT
CML
and V
V
TO
OUT
TO
C
2
OUT+
OUT-
pins
Equalization at the input compensates for high-frequency
loss encountered with FR4 stripline (edge-coupled) or
28AWG twin ax. The equalizer core is an amplifier with a
self-adjusting frequency response.
The DC cancellation loop removes the pulse-width dis-
tortion caused by internal offsets. The closed-loop
response creates a low-frequency cutoff of approxi-
mately 15kHz, below which the offset control tracks the
AC signal. This also sets the limit on the maximum time
Figure 3. CML Input Structure
Figure 4. CML Output Structure
STRUCTURES
IN+
IN-
ESD
V
CC
50Ω
+1.1V ≤ V
50Ω
+1.1V ≤ V
TO
≤ V
CC
50Ω
TI
≤ V
DC Cancellation Loop
CC
50Ω
Media Equalization
V
CC
V
CC
V
CC
STRUCTURES
ESD
OUT+
OUT-