DS1004M-3 Maxim Integrated, DS1004M-3 Datasheet

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DS1004M-3

Manufacturer Part Number
DS1004M-3
Description
Delay Lines / Timing Elements
Manufacturer
Maxim Integrated
Datasheet

Specifications of DS1004M-3

Function
Active Tapped Delay Line
Package / Case
PDIP-8 Narrow
Maximum Operating Temperature
+ 70 C
Minimum Operating Temperature
0 C
Mounting Style
Through Hole
Supply Voltage - Max
5.25 V
Supply Voltage - Min
4.75 V
Part # Aliases
90-1004M-003
FEATURES
DESCRIPTION
The DS1004 is a 5-tap all silicon delay line which can provide 2, 3, 4, or 5 ns tap-to-tap delays within a
standard part family. The device is Dallas Semiconductor’s fastest 5-tap delay line. It is available in a
standard 8-pin DIP and 150 mil 8-pin mini-SOIC. The device features precise leading and trailing edge
accuracies and has the inherent reliability of an all-silicon delay line solution.
The DS1004 is specified for tap-to-tap tolerances as shown in Table 1. Each device has a minimum
input-to-tap 1 delay of 5 ns. Subsequent taps (taps 2 through 5) are precisely delayed by 2, 3, 4, or 5 ns.
See Table 1 for details. Input to Tap Tolerance over temperature and voltage is 1.5 ns in addition to the
nominal delay tolerance. Nominal tap-to-tap tolerances range from 0.75 ns to 1.0 ns. Each output is
capable of driving up to 10 LS loads.
For customers needing non-standard delay values, the Late Package Program (LPP) is available.
Customers may contact Dallas Semiconductor at (972) 371–4348 for further details.
www.dalsemi.com
All-silicon timing circuit
Five delayed clock phases per input
Precise tap-to-tap nominal delay tolerances of
±0.75 and ±1 ns
Input-to-tap 1 delay of 5 ns
Nominal Delay tolerances of ±1.5 ns
Leading and trailing edge precision preserves
the input symmetry
CMOS design with TTL compatibility
Standard 8-pin DIP and 150 mil 8-pin SOIC
Vapor phase, IR and wave solderable
Available in Tape and Reel
1 of 6
PIN ASSIGNMENT
PIN DESCRIPTION
TAP 1-5
V
GND
IN
CC
TAP 2
TAP 2
TAP 4
TAP 4
DS1004M 8-Pin DIP (300-mil)
DS1004Z 8-Pin SOIC (150-mil)
GND
GND
See Mech. Drawings Section
See Mech. Drawings Section
IN
IN
1
2
3
4
1
2
3
4
- TAP Output Number
- +5V Supply
- Ground
- Input
Silicon Delay Line
5-Tap High Speed
8
7
6
5
8
7
6
5
V
V
TAP 1
TAP 3
TAP 5
TAP 1
TAP 3
TAP 5
CC
CC
DS1004
092500

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DS1004M-3 Summary of contents

Page 1

... High Speed Silicon Delay Line PIN ASSIGNMENT TAP 2 7 TAP 1 TAP TAP 3 GND 4 5 TAP 5 DS1004M 8-Pin DIP (300-mil) See Mech. Drawings Section TAP 1 TAP 2 TAP TAP 3 5 GND 4 TAP 5 DS1004Z 8-Pin SOIC (150-mil) See Mech ...

Page 2

... Temperature and voltage variations cover the range from + Delay accuracy for both leading and trailing edges. PART NUMBER DELAY TABLE Table 2 PART INPUT-TO- NUMBER TAP1 DS1004M DS1004M DS1004M DS1004M DS1004Z DS1004Z DS1004Z-4 ...

Page 3

DS1004 TEST CIRCUIT Figure 1 TEST SETUP DESCRIPTION Figure 1 illustrates the hardware configuration used for measuring the timing parameters of the DS1004. The input waveform is produced by a precision pulse generator under software control. Time delays are measured ...

Page 4

ABSOLUTE MAXIMUM RATINGS* Voltage on Any Pin Relative to Ground Operating Temperature Storage Temperature Soldering Temperature Short Circuit Output Current * This is a stress rating only and functional operation of the device at these or any other conditions above ...

Page 5

NOTES: 1. All voltages are referenced to ground =5V and 25 C. Delay accuracy on both the rising and falling edges within tolerances given in CC Table 1. 3. Pulse width and duty cycle specifications may be exceeded, ...

Page 6

TERMINOLOGY Period: The time elapsed between the leading edge of the first pulse and the leading edge of the following pulse. t (Pulse Width): The elapsed time on the pulse between the 1.5V point on the leading edge and the ...

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