91305AGILF IDT, 91305AGILF Datasheet

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91305AGILF

Manufacturer Part Number
91305AGILF
Description
Clock Drivers & Distribution
Manufacturer
IDT
Datasheet

Specifications of 91305AGILF

Product Category
Clock Drivers & Distribution
Rohs
yes
Part # Aliases
ICS91305AGILF
High Performance Communication Buffer
General Description
Block Diagram
0092H—12/02/08
The ICS91305 is a high performance, low skew, low jitter
clock driver. It uses a phase lock loop (PLL) technology
to align, in both phase and frequency, the REF input with
the CLKOUT signal. It is designed to distribute high speed
clocks in communication systems operating at speeds
from 10 to 133 MHz.
ICS91305 is a zero delay buffer that provides
synchronization between the input and output. The
synchronization is established via CLKOUT feed back to
the input of the PLL. Since the skew between the input and
output is less than +/- 350 pS, the part acts as a zero delay
buffer.
The ICS91305 comes in an eight pin 150 mil SOIC
package. It has five output clocks. In the absence of REF
input, will be in the power down mode. In this mode, the
PLL is turned off and the output buffers are pulled low.
Power down mode provides the lowest power consumption
for a standby condition.
Integrated
Circuit
Systems, Inc.
Features
Zero input - output delay
Frequency range 10 - 133 MHz (3.3V)
5V tolerant input REF
High loop filter bandwidth ideal for Spread
Spectrum applications.
Less than 200 ps Jitter between outputs
Skew controlled outputs
Skew less than 250 ps between outputs
Available in 8 pin 150 mil SOIC & 173 mil
TSSOP packages
3.3V ±10% operation
CLK2
CLK1
GND
REF
8 pin SOIC & TSSOP
Pin Configuration
1
2
3
4
8
7
6
5
ICS91305
CLKOUT
CLK4
VDD
CLK3

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91305AGILF Summary of contents

Page 1

... Zero input - output delay • Frequency range 10 - 133 MHz (3.3V) • 5V tolerant input REF • High loop filter bandwidth ideal for Spread Spectrum applications. • Less than 200 ps Jitter between outputs • Skew controlled outputs • Skew less than 250 ps between outputs • ...

Page 2

ICS91305 Pin Descriptions ...

Page 3

Absolute Maximum Ratings Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . 7.0 V Logic Inputs (Except REF ...

Page 4

ICS91305 Switching Characteristics ...

Page 5

Output to Output Skew The skew between CLKOUT and the CLK(1-4) outputs is not dynamically adjusted by the PLL. Since CLKOUT is one of the inputs to the PLL, zero phase difference is maintained from REF to CLKOUT. If all ...

Page 6

ICS91305 N INDE X ARE 150 mil (Narrow Body) SOIC Ordering Information 91305yMLFT Example: XXXX Designation for tape and reel packaging Lead Free, ROHS Compliant (Optional) Package Type ...

Page 7

N E1 INDEX AREA Ordering Information 91305yGLFT Example: XXXX 0092H—12/02/08 c SYMBOL α aaa ...

Page 8

ICS91305 Revision History Rev. Issue Date Description G 8/6/2007 Updated Rise/Fall Time. H 12/2/2008 Removed ICS prefix from ordering information 0092H—12/02/08 Page # 6 ...

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