ZR36067PQC ETC [List of Unclassifed Manufacturers], ZR36067PQC Datasheet - Page 11

• Manufacturer Part Number: ZR36067PQC
• Description: AV PCI CONTROLLER
• Manufacturer: ETC [List of Unclassifed Manufacturers]

the extended 24-bit video bus and the synchronization signals in
order to drive the pixels to the ZR36016 or get them from it, as
appropriate.
The following four subsections detail the four basic functions of
the Video Interface:
5.2.1 Sampling The Incoming Video
The ZR36067’s Video Front End (VFE) interfaces to a standard
YUV 4:2:2 video bus. It samples the Y7..0, UV7..0, HSYNC and
VSYNC with every other positive edge of VCLKx2. The valid
positive edge (out of every two consecutive ones), which is the
one used for sampling, is qualified by VCLK. The qualifying
polarity of VCLK is configured by the host. This scheme makes
the ZR36067 compatible with a wide range of digital video
sources and immune to board-level parasitic delays. VCLKx2
(positive edges) is used internally in the video processing
pipeline.
The VFE generates a field indication signal targeted to some
internal video processing units. There are two alternative ways
of generating the field indication. With devices that output a field
indication, the VFE uses the FI input as an indicator of the
current field identity. The interpretation of the logical level of FI
(top or bottom field) is configured by the host. With devices that
do not provide such an indication, the VFE infers the field identity
from the relationship of HSYNC to VSYNC.
The VFE can capture square pixel and CCIR-601 formats, or
user defined formats, within the limitation of its parameters. The
maximum theoretical total input resolution is 1023 pixels/line x
1023 lines per frame. Cropping of the input image is possible by
proper configuration of the VFE parameters.
Table 1 lists the Video Front End parameters. The host software
needs to configure these parameters according to the timing
parameters of the video source (e.g., SAA7110, SAA7111,
ZR36060, etc.) and the required cropping. Note that these
parameters relate to the input video, and not to the destination
video window.
Table 1: Video Front-End Parameters
VStart
HStart
VEnd
• Sampling the incoming video.
• Generating the synchronization signals.
• Pixel transfer in Still Image Compression.
• Pixel transfer in Still Image Decompression.
Parameter
itive or negative, according to VSPol) of VSYNC to the
first line to be sampled.
HSYNC until the first pixel to be sampled.
itive or negative, according to VSPol) of VSYNC to the
last line to be sampled.
Number of lines (HSYNCs) from the active edge (pos-
Number of pixel clocks in a line from the active edge of
Number of lines (HSYNCs) from the active edge (pos-
Description
11
Table 1: Video Front-End Parameters
5.2.2 Synchronization Signal Generation
The ZR36067 supports internal generation of the video synchro-
nization signals. In this mode (when SyncMstr =1) the ZR36067
generates and drives VSYNC and HSYNC signals. Using
software programmable parameters, the ZR36067 can generate
various video synchronization signal formats.
Table 3 lists the sync signal parameters. The host software con-
figures those parameters according the mode of operation and
the video peripheral devices used. Note that he polarity of the
sync signals is determined by the VSPol and HSPol parameters
(Table 2).
Table 2: Synchronization Signal Parameters
HEnd
ExtFI
HSPol
VSPol
TopField
VCLKPol
FrmTot
LineTot
VsyncSize
Hsync Start
Parameter
Parameter
Number of pixel clocks in a line from the active edge of
HSYNC until the last pixel to be sampled.
This one bit parameter indicates whether the video
source provides a field indication signal.
The HSYNC polarity. HStart and HEnd are counted
from the active edge of HSYNC. ‘1’ means that HStart,
HEnd will be counted from the negative edge of
HSYNC. Also determines signal polarity when
SyncMstr=’1’.
The VSYNC polarity. VStart and VEnd are counted
from the active edge of VSYNC. ‘1’ means that VStart,
VEnd will be counted from the negative edge of
VSYNC. Also determines signal polarity when
SyncMstr=’1’.
Top Field Interpretation. If field indication is derived
from the FI input signal (see ExtFI), TopField indicates
the interpretation of the FI signal:
TopField=‘1’ - FI high indicates the top field.
TopField=‘0’ - FI low indicates the top field.
If field indication is derived internally from HSYNC and
VSYNC, TopField indicates the interpretation of the
level of HSYNC as sampled by the active edge of
VSYNC:
TopField=‘1’ - HSYNC high indicates the top field.
TopField=‘0’ - HSYNC low indicates the top field.
Polarity of VCLK as a data qualifier. If VCLKPol=1 the
video input is sampled with those positive edges of
VCLKx2 that correspond to VCLK=1. If VCLKPol=0,
the video input is sampled by those positive edges of
VCLKx2 that correspond to VCLK=0.
Total number of lines per frame
(e.g., in NTSC: 525)
Total number of pixel clocks per line
(e.g., in CCIR NTSC: 858)
lines.
signal should be asserted.
The length of the VSYNC signal, measured in
The point in the scan line at which the HSYNC
AV PCI CONTROLLER
Description
Meaning