LC89057W-VF4A-E SANYO [Sanyo Semicon Device], LC89057W-VF4A-E Datasheet - Page 47

• Manufacturer Part Number: LC89057W-VF4A-E
• Description: Digital Audio Interface Transceiver
• Manufacturer: SANYO [Sanyo Semicon Device]

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For Non-PCM data, the data defined with AOSEL is reflected. In other words, it is identical to the detected data output
Output data is muted if an error occurs due to non-PCM data with RESEL.
The RESTA setting is not reflected to the output pins of data and clock.
For FSERR, the fs calculation result obtained while the oscillation amplifier is stopped is not reflected. In this case, fs
ERWT[1:0] defines the interval of time for RERR to output error cancellation ("L") after PLL is locked. Since
to
changes consist of only channel status fs information.
demodulated audio data is output after RERR cancels an error, you need to change this setting if the situation that the
head of data is missing is a problem.
AUDIO.
____________
RESEL
REDER
XTWT [1:0]
RESTA
FSERR
ERWT [1:0]
CCB address: 0xE8, Command address: 9; Demodulation function: RERR output setting
ERWT1
DI15
DI7
1
ERWT0
DI14
DI6
0
RERR output contents setting
0: PLL lock error or data error (initial value)
1: PLL lock error or data error or non-PCM data
Setting of parity error flag output within 8 times in a row
0: Output only when non-PCM data is recognized (initial value)
1: Output only during sub-frame for which error was generated
Setting of clock switch wait time after PLL is unlocked
00: Clock switching after approx. 200μs from when oscillation amplifier starts
01: Clock switching after approx. 100μs from when oscillation amplifier starts
10: Clock switching after approx. 50μs from when oscillation amplifier starts
11: Clock switching after PLL is unlocked
RERR output condition setting
0: Output PLL status all the time (Output PLL status even during XIN source)
1: Forcibly output error (Set "H" to RERR forcibly)
Setting of error flag output condition according to fs change
0: Reflect fs changes to error flag (initial value)
1: Don't reflect fs changes to error flag
Setting of RERR wait time after PLL is locked
00: Cancel error after preamble B is counted 3 (initial value)
01: Cancel error after preamble B is counted 24
10: Cancel error after preamble B is counted 12
11: Cancel error after preamble B is counted 6
(initial status)
(initial value)
FSERR
DI13
DI5
0
LC89057W-VF4A-E
RESTA
DI12
DI4
1
XTWT1
DI11
DI3
0
XTWT0
DI10
DI2
0
REDER
CAU
DI1
DI9
RESEL
CAL
DI0
DI8
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