ELANSC300 AMD [Advanced Micro Devices], ELANSC300 Datasheet

ELANSC300

Manufacturer Part Number

ELANSC300

Description

Highly Integrated, Low-Power, 32-Bit Microcontroller

Manufacturer

AMD [Advanced Micro Devices]

Datasheet

1.ELANSC300.pdf (139 pages)

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Élan

Highly Integrated, Low-Power, 32-Bit Microcontroller

DISTINCTIVE CHARACTERISTICS

This document contains information on a product under development at Advanced Micro Devices. The information

is intended to help you evaluate this product. AMD reserves the right to change or discontinue work on this product

without notice.

Highly integrated, single-chip CPU and system

logic

– Optimized for embedded PC applications

– Combines 32 bit, x86 compatible, low-voltage

– 0.7 micron, low-voltage, CMOS process, fully

Enhanced Am386 ® SXLV CPU core

– 25 MHz or 33 MHz operating frequencies

– 3.3 V core, 3.3 V or 5 V memory and I/O

– Low-power, fully static design for long battery life

– System Management Mode (SMM) for power

– Internal clock generators (using multiple Phase-

– Supports CPU System Management Mode

– Multiple operating modes: High Speed PLL, Low

– Comprehensive control of system and peripheral

– Five external power management control pins

– Suspend refresh of DRAM array

– Clock switching during ISA cycles

– Low power consumption: 0.12 mW typical

– Simultaneous multiple-voltage I/O pads operate

Integrated memory controller

– Controls symmetrically addressable DRAM or

Integrated power management functions

CPU with memory controller, PC/AT peripheral

controllers, real-time clock, and PLL clock gener-

ators

static

management control

Locked Loops and one external 32-KHz crystal)

(SMM)

Speed PLL, Doze, Sleep, Suspend, and Off. Fully

static design allows stopped clock.

clocks

Suspend mode power

at either 3.3 V or 5 V. Core operates at 3.3 V for

minimum power consumption.

asymmetrical 512 Kbyte x 8 bit or 1 Mbyte x 16 bit

DRAM or SRAM as main memory

PRELIMINARY

™

SC300

– Zero wait-state access with 70 ns, Page mode

– Supports up to 16 Mbyte system memory

– Supports up to 16 Mbyte of application ROM/

– Fully PC/AT compatible

Integrated PC/AT-compatible peripheral logic

– One programmable interval timer (fully 8254

– Two programmable interrupt controllers (8259A

– Two DMA controllers (8237A compatible)

– Built-in real-time clock (146818A compatible),

– Internal Phase-Locked Loops (PLL) generate all

Bus configurations

– 16-bit data path

– Optional bus configurations:

– Four programmable chip selects

– Built-in 8042 chip select

Serial port controller (16450 UART compatible)

Bidirectional parallel port with EPP

Integrates two PCMCIA Version 2.1 slots

Integrated CGA-compatible LCD controller

– Fully 6845 compatible

– 16 gray levels in Text mode; 2 or 4 levels in

– Supports the following LCD Panel Sizes:

DRAMs

Flash, and 320 Kbyte direct ROM BIOS access.

Also supports shadow RAM

compatible)

with an additional 114 bytes of RAM

clocks from single 32.768 kHz crystal input

Graphics mode

— Internal LCD controller with subset ISA

— 386 Local Bus mode with subset ISA

— Maximum ISA Bus mode

— 320 x 240 single scan (2 bpp)

— 640 x 200 single/dual scan (1 bpp)

— 480 x 320 single scan (1 bpp)

Publication# 18514

Issue Date: October 1997

Rev: D Amendment/0

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