EDD2508AKTA-5B ELPIDA [Elpida Memory], EDD2508AKTA-5B Datasheet - Page 32

• Manufacturer Part Number: EDD2508AKTA-5B
• Description: 256M bits DDR SDRAM (32M words x 8 bits, DDR400)
• Manufacturer: ELPIDA [Elpida Memory]

A Write command to the consecutive Read command interval: To complete the burst operation
1. Same
2. Same
3. Different
Preliminary Data Sheet E0349E60 (Ver. 6.0)
Command
Note: tWTR is referenced from the first positive CK edge after the last desired data in pair tWTR.
Destination row of the consecutive read
command
Bank
address
DQS
/CK
DM
DQ
CK
WRIT
Row address State
Same
Different
Any
t0
in0
t1
ACTIVE
—
ACTIVE
IDLE
INPUT
BL/2 + 2 cycle
in1
tWRD (min)
NOP
in2
WRITE to READ Command Interval
t2
Operation
To complete the burst operation, the consecutive read command should be
performed tWRD (= BL/ 2 + 2) after the write command.
Precharge the bank tWPD after the preceding write command. tRP after the
precharge command, issue the ACT command. tRCD after the ACT command, the
consecutive read command can be issued. See ‘A read command to the
consecutive precharge interval’ section.
To complete a burst operation, the consecutive read command should be
performed tWRD (= BL/ 2 + 2) after the write command.
Precharge the bank independently of the preceding write operation. tRP after the
precharge command, issue the ACT command. tRCD after the ACT command, the
consecutive read command can be issued.
in3
t3
tWTR*
32
READ
t4
t5
t6
EDD2508AKTA-5
NOP
t7
OUTPUT
out0
out1
t8
BL = 4
CL = 3
out2